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authorClifford Wolf <clifford@clifford.at>2014-07-22 20:58:44 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-22 20:58:44 +0200
commit28b3fd05fa9cf6d469fdec95e247a7ffe5bc001d (patch)
tree9a847fc2fc608ce9ffbc947bcb18eea2205bb2d5 /passes/techmap/extract.cc
parent7bffde6abdaf6fc2ed090946442f90b2438e6126 (diff)
SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()
Diffstat (limited to 'passes/techmap/extract.cc')
-rw-r--r--passes/techmap/extract.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index a960f2ba..5a729808 100644
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -756,7 +756,7 @@ struct ExtractPass : public Pass {
newCell->parameters = cell->parameters;
for (auto &conn : cell->connections) {
RTLIL::SigSpec sig = sigmap(conn.second);
- for (auto &chunk : sig.chunks())
+ for (auto &chunk : sig.chunks_rw())
if (chunk.wire != NULL)
chunk.wire = newMod->wires.at(chunk.wire->name);
newCell->connections[conn.first] = sig;