diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-07-27 01:51:45 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-27 01:51:45 +0200 |
| commit | 4c4b6021562c598c4510831bd547edaa97d14dac (patch) | |
| tree | 7d8bde9d617e67431bdb6c51b5e27ea1836fe7a5 /passes/techmap/extract.cc | |
| parent | f9946232adf887e5aa4a48c64f88eaa17e424009 (diff) | |
Refactoring: Renamed RTLIL::Module::cells to cells_
Diffstat (limited to 'passes/techmap/extract.cc')
| -rw-r--r-- | passes/techmap/extract.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index 813e0e3e..b66a11b8 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -182,7 +182,7 @@ namespace std::map<std::pair<RTLIL::Wire*, int>, int> sig_use_count; if (max_fanout > 0) - for (auto &cell_it : mod->cells) + for (auto &cell_it : mod->cells_) { RTLIL::Cell *cell = cell_it.second; if (!sel || sel->selected(mod, cell)) @@ -196,7 +196,7 @@ namespace } // create graph nodes from cells - for (auto &cell_it : mod->cells) + for (auto &cell_it : mod->cells_) { RTLIL::Cell *cell = cell_it.second; if (sel && !sel->selected(mod, cell)) @@ -253,7 +253,7 @@ namespace } // mark external signals (used in non-selected cells) - for (auto &cell_it : mod->cells) + for (auto &cell_it : mod->cells_) { RTLIL::Cell *cell = cell_it.second; if (sel && !sel->selected(mod, cell)) |