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authorClifford Wolf <clifford@clifford.at>2014-07-23 08:40:31 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-23 09:49:43 +0200
commita8d3a68971ccc4e47c54a906aae374a9a54b1415 (patch)
treeed08831d07df4e799d881349c36acf76bf277791 /passes/techmap/extract.cc
parent260c19ec5a3adb292158658dd69a352b9325ab64 (diff)
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3
Diffstat (limited to 'passes/techmap/extract.cc')
-rw-r--r--passes/techmap/extract.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index 5a729808..988917b1 100644
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -315,7 +315,7 @@ namespace
RTLIL::Wire *wire = it.second;
if (wire->port_id > 0) {
for (int i = 0; i < wire->width; i++)
- sig2port.insert(sigmap(RTLIL::SigSpec(wire, 1, i)), std::pair<std::string, int>(wire->name, i));
+ sig2port.insert(sigmap(RTLIL::SigSpec::grml(wire, i)), std::pair<std::string, int>(wire->name, i));
cell->connections[wire->name] = RTLIL::SigSpec(RTLIL::State::Sz, wire->width);
}
}