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authorClifford Wolf <clifford@clifford.at>2014-07-26 21:16:05 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-26 21:30:38 +0200
commitd68c993ed2ea384db4d6af5161b3b36096828499 (patch)
tree4f1259436d3d8f73eb21f1a29662826a24cedf4c /passes/techmap/extract.cc
parent946ddff9cef3ea0b4dad8664319fb13074133775 (diff)
Changed more code to the new RTLIL::Wire constructors
Diffstat (limited to 'passes/techmap/extract.cc')
-rw-r--r--passes/techmap/extract.cc5
1 files changed, 1 insertions, 4 deletions
diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index b8c349f5..92bcafc0 100644
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -729,13 +729,10 @@ struct ExtractPass : public Pass {
int portCounter = 1;
for (auto wire : wires) {
- RTLIL::Wire *newWire = new RTLIL::Wire;
- newWire->name = wire->name;
- newWire->width = wire->width;
+ RTLIL::Wire *newWire = newMod->addWire(wire->name, wire->width);
newWire->port_id = portCounter++;
newWire->port_input = true;
newWire->port_output = true;
- newMod->add(newWire);
}
for (auto cell : cells) {