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authorClifford Wolf <clifford@clifford.at>2014-07-23 09:48:26 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-23 09:52:55 +0200
commitec923652e2eb721aa16657e54a67666f855c3d65 (patch)
tree934ce8ee55c3c58a1e2c11f19eec194665413906 /passes/techmap/extract.cc
parenta8d3a68971ccc4e47c54a906aae374a9a54b1415 (diff)
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3
Diffstat (limited to 'passes/techmap/extract.cc')
-rw-r--r--passes/techmap/extract.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index 988917b1..1687a1ff 100644
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -315,7 +315,7 @@ namespace
RTLIL::Wire *wire = it.second;
if (wire->port_id > 0) {
for (int i = 0; i < wire->width; i++)
- sig2port.insert(sigmap(RTLIL::SigSpec::grml(wire, i)), std::pair<std::string, int>(wire->name, i));
+ sig2port.insert(sigmap(RTLIL::SigSpec(wire, i)), std::pair<std::string, int>(wire->name, i));
cell->connections[wire->name] = RTLIL::SigSpec(RTLIL::State::Sz, wire->width);
}
}