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authorClifford Wolf <clifford@clifford.at>2014-07-27 01:49:51 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-27 01:49:51 +0200
commitf9946232adf887e5aa4a48c64f88eaa17e424009 (patch)
tree39594b3287c3369752668456c4a6b1735fb66e77 /passes/techmap/extract.cc
parentd7916a49aff3c47b7c1ce07abe3b6e3d5714079b (diff)
Refactoring: Renamed RTLIL::Module::wires to wires_
Diffstat (limited to 'passes/techmap/extract.cc')
-rw-r--r--passes/techmap/extract.cc6
1 files changed, 3 insertions, 3 deletions
diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index 92bcafc0..813e0e3e 100644
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -271,7 +271,7 @@ namespace
}
// mark external signals (used in module ports)
- for (auto &wire_it : mod->wires)
+ for (auto &wire_it : mod->wires_)
{
RTLIL::Wire *wire = wire_it.second;
if (wire->port_id > 0)
@@ -300,7 +300,7 @@ namespace
RTLIL::Cell *cell = haystack->addCell(stringf("$extract$%s$%d", needle->name.c_str(), RTLIL::autoidx++), needle->name);
// create cell ports
- for (auto &it : needle->wires) {
+ for (auto &it : needle->wires_) {
RTLIL::Wire *wire = it.second;
if (wire->port_id > 0) {
for (int i = 0; i < wire->width; i++)
@@ -742,7 +742,7 @@ struct ExtractPass : public Pass {
std::vector<RTLIL::SigChunk> chunks = sigmap(conn.second);
for (auto &chunk : chunks)
if (chunk.wire != NULL)
- chunk.wire = newMod->wires.at(chunk.wire->name);
+ chunk.wire = newMod->wires_.at(chunk.wire->name);
newCell->set(conn.first, chunks);
}
}