diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-07-22 20:58:44 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-22 20:58:44 +0200 |
| commit | 28b3fd05fa9cf6d469fdec95e247a7ffe5bc001d (patch) | |
| tree | 9a847fc2fc608ce9ffbc947bcb18eea2205bb2d5 /passes/techmap/hilomap.cc | |
| parent | 7bffde6abdaf6fc2ed090946442f90b2438e6126 (diff) | |
SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()
Diffstat (limited to 'passes/techmap/hilomap.cc')
| -rw-r--r-- | passes/techmap/hilomap.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/hilomap.cc b/passes/techmap/hilomap.cc index ac41e47c..53c5d104 100644 --- a/passes/techmap/hilomap.cc +++ b/passes/techmap/hilomap.cc @@ -31,7 +31,7 @@ static RTLIL::SigChunk last_hi, last_lo; void hilomap_worker(RTLIL::SigSpec &sig) { sig.expand(); - for (auto &c : sig.chunks()) { + for (auto &c : sig.chunks_rw()) { if (c.wire == NULL && (c.data.bits.at(0) == RTLIL::State::S1) && !hicell_celltype.empty()) { if (!singleton_mode || last_hi.width == 0) { last_hi = RTLIL::SigChunk(module->addWire(NEW_ID)); |