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authorClifford Wolf <clifford@clifford.at>2014-07-25 15:05:18 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-25 17:56:19 +0200
commit2bec47a4045d23d46e7d300cbf80b2dce1a549a9 (patch)
tree991a75afe9b009486a57834fefee075ec695a28c /passes/techmap/hilomap.cc
parent5826670009e1018734de49aaf1554cb8a43d09d7 (diff)
Use only module->addCell() and module->remove() to create and delete cells
Diffstat (limited to 'passes/techmap/hilomap.cc')
-rw-r--r--passes/techmap/hilomap.cc10
1 files changed, 2 insertions, 8 deletions
diff --git a/passes/techmap/hilomap.cc b/passes/techmap/hilomap.cc
index 51b8802c..e4153670 100644
--- a/passes/techmap/hilomap.cc
+++ b/passes/techmap/hilomap.cc
@@ -34,22 +34,16 @@ void hilomap_worker(RTLIL::SigSpec &sig)
if (bit == RTLIL::State::S1 && !hicell_celltype.empty()) {
if (!singleton_mode || last_hi == RTLIL::State::Sm) {
last_hi = module->addWire(NEW_ID);
- RTLIL::Cell *cell = new RTLIL::Cell;
- cell->name = NEW_ID;
- cell->type = RTLIL::escape_id(hicell_celltype);
+ RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(hicell_celltype));
cell->connections[RTLIL::escape_id(hicell_portname)] = last_hi;
- module->add(cell);
}
bit = last_hi;
}
if (bit == RTLIL::State::S0 && !locell_celltype.empty()) {
if (!singleton_mode || last_lo == RTLIL::State::Sm) {
last_lo = module->addWire(NEW_ID);
- RTLIL::Cell *cell = new RTLIL::Cell;
- cell->name = NEW_ID;
- cell->type = RTLIL::escape_id(locell_celltype);
+ RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(locell_celltype));
cell->connections[RTLIL::escape_id(locell_portname)] = last_lo;
- module->add(cell);
}
bit = last_lo;
}