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authorClifford Wolf <clifford@clifford.at>2014-07-21 12:41:29 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-21 12:42:02 +0200
commit361e0d62ffd90b87c94bfc98ed3cbee1a745cd8f (patch)
tree59c594e41320db3a58677857f30c21688427981d /passes/techmap/hilomap.cc
parent1d88f1cf9f2088de7825f5292db5b40d4f73d036 (diff)
Replaced depricated NEW_WIRE macro with module->addWire() calls
Diffstat (limited to 'passes/techmap/hilomap.cc')
-rw-r--r--passes/techmap/hilomap.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/techmap/hilomap.cc b/passes/techmap/hilomap.cc
index bc5caa38..d24f557e 100644
--- a/passes/techmap/hilomap.cc
+++ b/passes/techmap/hilomap.cc
@@ -34,7 +34,7 @@ void hilomap_worker(RTLIL::SigSpec &sig)
for (auto &c : sig.chunks) {
if (c.wire == NULL && (c.data.bits.at(0) == RTLIL::State::S1) && !hicell_celltype.empty()) {
if (!singleton_mode || last_hi.width == 0) {
- last_hi = RTLIL::SigChunk(NEW_WIRE(module, 1));
+ last_hi = RTLIL::SigChunk(module->addWire(NEW_ID));
RTLIL::Cell *cell = new RTLIL::Cell;
cell->name = NEW_ID;
cell->type = RTLIL::escape_id(hicell_celltype);
@@ -45,7 +45,7 @@ void hilomap_worker(RTLIL::SigSpec &sig)
}
if (c.wire == NULL && (c.data.bits.at(0) == RTLIL::State::S0) && !locell_celltype.empty()) {
if (!singleton_mode || last_lo.width == 0) {
- last_lo = RTLIL::SigChunk(NEW_WIRE(module, 1));
+ last_lo = RTLIL::SigChunk(module->addWire(NEW_ID));
RTLIL::Cell *cell = new RTLIL::Cell;
cell->name = NEW_ID;
cell->type = RTLIL::escape_id(locell_celltype);