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authorClifford Wolf <clifford@clifford.at>2014-07-23 15:36:09 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-23 15:36:09 +0200
commit4e802eb7f6fe5858f8657be7cd3e6638cc0f2ece (patch)
tree917ce7eece77475cfc632f3d41f5fb8aadef64d2 /passes/techmap/hilomap.cc
parent85db102e13bbd6decda3f99ef640d0991ee24b33 (diff)
Fixed all users of SigSpec::chunks_rw() and removed it
Diffstat (limited to 'passes/techmap/hilomap.cc')
-rw-r--r--passes/techmap/hilomap.cc26
1 files changed, 12 insertions, 14 deletions
diff --git a/passes/techmap/hilomap.cc b/passes/techmap/hilomap.cc
index 53c5d104..51b8802c 100644
--- a/passes/techmap/hilomap.cc
+++ b/passes/techmap/hilomap.cc
@@ -26,36 +26,34 @@ static std::string locell_celltype, locell_portname;
static bool singleton_mode;
static RTLIL::Module *module;
-static RTLIL::SigChunk last_hi, last_lo;
+static RTLIL::SigBit last_hi, last_lo;
void hilomap_worker(RTLIL::SigSpec &sig)
{
- sig.expand();
- for (auto &c : sig.chunks_rw()) {
- if (c.wire == NULL && (c.data.bits.at(0) == RTLIL::State::S1) && !hicell_celltype.empty()) {
- if (!singleton_mode || last_hi.width == 0) {
- last_hi = RTLIL::SigChunk(module->addWire(NEW_ID));
+ for (auto &bit : sig) {
+ if (bit == RTLIL::State::S1 && !hicell_celltype.empty()) {
+ if (!singleton_mode || last_hi == RTLIL::State::Sm) {
+ last_hi = module->addWire(NEW_ID);
RTLIL::Cell *cell = new RTLIL::Cell;
cell->name = NEW_ID;
cell->type = RTLIL::escape_id(hicell_celltype);
cell->connections[RTLIL::escape_id(hicell_portname)] = last_hi;
module->add(cell);
}
- c = last_hi;
+ bit = last_hi;
}
- if (c.wire == NULL && (c.data.bits.at(0) == RTLIL::State::S0) && !locell_celltype.empty()) {
- if (!singleton_mode || last_lo.width == 0) {
- last_lo = RTLIL::SigChunk(module->addWire(NEW_ID));
+ if (bit == RTLIL::State::S0 && !locell_celltype.empty()) {
+ if (!singleton_mode || last_lo == RTLIL::State::Sm) {
+ last_lo = module->addWire(NEW_ID);
RTLIL::Cell *cell = new RTLIL::Cell;
cell->name = NEW_ID;
cell->type = RTLIL::escape_id(locell_celltype);
cell->connections[RTLIL::escape_id(locell_portname)] = last_lo;
module->add(cell);
}
- c = last_lo;
+ bit = last_lo;
}
}
- sig.optimize();
}
struct HilomapPass : public Pass {
@@ -119,8 +117,8 @@ struct HilomapPass : public Pass {
if (!design->selected(module))
continue;
- last_hi = RTLIL::SigChunk();
- last_lo = RTLIL::SigChunk();
+ last_hi = RTLIL::State::Sm;
+ last_lo = RTLIL::State::Sm;
module->rewrite_sigspecs(hilomap_worker);
}