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authorClifford Wolf <clifford@clifford.at>2014-07-22 19:56:17 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-22 20:39:37 +0200
commita233762a815fc180b371f699e865a7d7aed77bca (patch)
tree722e54921bbc09595c046c6045cd531445945fc9 /passes/techmap/hilomap.cc
parent3b5f4ff39c94a5a664043f35b95a50240ffe9d12 (diff)
SigSpec refactoring: renamed chunks and width to __chunks and __width
Diffstat (limited to 'passes/techmap/hilomap.cc')
-rw-r--r--passes/techmap/hilomap.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/hilomap.cc b/passes/techmap/hilomap.cc
index d24f557e..22f4c7d1 100644
--- a/passes/techmap/hilomap.cc
+++ b/passes/techmap/hilomap.cc
@@ -31,7 +31,7 @@ static RTLIL::SigChunk last_hi, last_lo;
void hilomap_worker(RTLIL::SigSpec &sig)
{
sig.expand();
- for (auto &c : sig.chunks) {
+ for (auto &c : sig.__chunks) {
if (c.wire == NULL && (c.data.bits.at(0) == RTLIL::State::S1) && !hicell_celltype.empty()) {
if (!singleton_mode || last_hi.width == 0) {
last_hi = RTLIL::SigChunk(module->addWire(NEW_ID));