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authorClifford Wolf <clifford@clifford.at>2014-07-26 11:58:03 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-26 11:58:03 +0200
commitcc4f10883bcc5f0a3c1b4f0937e60be3c6a1b121 (patch)
tree2d417ab32f95d109a0d8438ae7a14acf51783c5b /passes/techmap/hilomap.cc
parent665759fceee4a0db3e776b7912e976eea2ff29a3 (diff)
Renamed RTLIL::{Module,Cell}::connections to connections_
Diffstat (limited to 'passes/techmap/hilomap.cc')
-rw-r--r--passes/techmap/hilomap.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/techmap/hilomap.cc b/passes/techmap/hilomap.cc
index e4153670..286ad8ac 100644
--- a/passes/techmap/hilomap.cc
+++ b/passes/techmap/hilomap.cc
@@ -35,7 +35,7 @@ void hilomap_worker(RTLIL::SigSpec &sig)
if (!singleton_mode || last_hi == RTLIL::State::Sm) {
last_hi = module->addWire(NEW_ID);
RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(hicell_celltype));
- cell->connections[RTLIL::escape_id(hicell_portname)] = last_hi;
+ cell->connections_[RTLIL::escape_id(hicell_portname)] = last_hi;
}
bit = last_hi;
}
@@ -43,7 +43,7 @@ void hilomap_worker(RTLIL::SigSpec &sig)
if (!singleton_mode || last_lo == RTLIL::State::Sm) {
last_lo = module->addWire(NEW_ID);
RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(locell_celltype));
- cell->connections[RTLIL::escape_id(locell_portname)] = last_lo;
+ cell->connections_[RTLIL::escape_id(locell_portname)] = last_lo;
}
bit = last_lo;
}