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authorClifford Wolf <clifford@clifford.at>2014-07-23 10:05:42 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-23 10:05:42 +0200
commit5b51b67297a5e5e20cbe2b015b584aee4c30489f (patch)
tree934ce8ee55c3c58a1e2c11f19eec194665413906 /passes/techmap/iopadmap.cc
parentc61467a32c4bd3ec4b9e0cb6d36d602f0e4dea81 (diff)
parentec923652e2eb721aa16657e54a67666f855c3d65 (diff)
Merge branch: Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor
Diffstat (limited to 'passes/techmap/iopadmap.cc')
-rw-r--r--passes/techmap/iopadmap.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc
index eb2757f6..09147383 100644
--- a/passes/techmap/iopadmap.cc
+++ b/passes/techmap/iopadmap.cc
@@ -179,9 +179,9 @@ struct IopadmapPass : public Pass {
RTLIL::Cell *cell = new RTLIL::Cell;
cell->name = NEW_ID;
cell->type = RTLIL::escape_id(celltype);
- cell->connections[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire, 1, i);
+ cell->connections[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire, i);
if (!portname2.empty())
- cell->connections[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire, 1, i);
+ cell->connections[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire, i);
if (!widthparam.empty())
cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(1);
if (!nameparam.empty())