diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-07-31 16:38:54 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-31 16:38:54 +0200 |
| commit | cdae8abe16847c533171fed111beea7b52202cce (patch) | |
| tree | bf8dddb4a4ca4d70c83603ef61b2d22cb95d153a /passes/techmap/iopadmap.cc | |
| parent | b5a9e51b966abdfedc9309defa79b5141928e84a (diff) | |
Renamed port access function on RTLIL::Cell, added param access functions
Diffstat (limited to 'passes/techmap/iopadmap.cc')
| -rw-r--r-- | passes/techmap/iopadmap.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc index 10627cd1..194e06a4 100644 --- a/passes/techmap/iopadmap.cc +++ b/passes/techmap/iopadmap.cc @@ -172,9 +172,9 @@ struct IopadmapPass : public Pass { for (int i = 0; i < wire->width; i++) { RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype)); - cell->set(RTLIL::escape_id(portname), RTLIL::SigSpec(wire, i)); + cell->setPort(RTLIL::escape_id(portname), RTLIL::SigSpec(wire, i)); if (!portname2.empty()) - cell->set(RTLIL::escape_id(portname2), RTLIL::SigSpec(new_wire, i)); + cell->setPort(RTLIL::escape_id(portname2), RTLIL::SigSpec(new_wire, i)); if (!widthparam.empty()) cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(1); if (!nameparam.empty()) @@ -185,9 +185,9 @@ struct IopadmapPass : public Pass { else { RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype)); - cell->set(RTLIL::escape_id(portname), RTLIL::SigSpec(wire)); + cell->setPort(RTLIL::escape_id(portname), RTLIL::SigSpec(wire)); if (!portname2.empty()) - cell->set(RTLIL::escape_id(portname2), RTLIL::SigSpec(new_wire)); + cell->setPort(RTLIL::escape_id(portname2), RTLIL::SigSpec(new_wire)); if (!widthparam.empty()) cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(wire->width); if (!nameparam.empty()) |