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authorClifford Wolf <clifford@clifford.at>2014-07-26 21:16:05 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-26 21:30:38 +0200
commitd68c993ed2ea384db4d6af5161b3b36096828499 (patch)
tree4f1259436d3d8f73eb21f1a29662826a24cedf4c /passes/techmap/iopadmap.cc
parent946ddff9cef3ea0b4dad8664319fb13074133775 (diff)
Changed more code to the new RTLIL::Wire constructors
Diffstat (limited to 'passes/techmap/iopadmap.cc')
-rw-r--r--passes/techmap/iopadmap.cc9
1 files changed, 2 insertions, 7 deletions
diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc
index 114d28e2..ab3bb3ed 100644
--- a/passes/techmap/iopadmap.cc
+++ b/passes/techmap/iopadmap.cc
@@ -164,13 +164,8 @@ struct IopadmapPass : public Pass {
log("Mapping port %s.%s using %s.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name), celltype.c_str());
RTLIL::Wire *new_wire = NULL;
- if (!portname2.empty()) {
- new_wire = new RTLIL::Wire;
- *new_wire = *wire;
- wire->name = NEW_ID;
- module->wires[wire->name] = wire;
- module->wires[new_wire->name] = new_wire;
- }
+ if (!portname2.empty())
+ new_wire = module->addWire(NEW_ID, wire);
if (flag_bits)
{