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authorClifford Wolf <clifford@clifford.at>2015-09-18 21:55:48 +0200
committerClifford Wolf <clifford@clifford.at>2015-09-18 21:55:48 +0200
commitc851f51656a80edd47eabc7fafbe69d56dea9fae (patch)
tree18f259f2b06952ca08905b270cedd56df215ee5b /passes/techmap/lut2mux.cc
parentd212d4d0c1b5fe4aef1e483c23466e439c8c4790 (diff)
Added lut2mux pass
Diffstat (limited to 'passes/techmap/lut2mux.cc')
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1 files changed, 93 insertions, 0 deletions
diff --git a/passes/techmap/lut2mux.cc b/passes/techmap/lut2mux.cc
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+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+int lut2mux(Cell *cell)
+{
+ SigSpec sig_a = cell->getPort("\\A");
+ SigSpec sig_y = cell->getPort("\\Y");
+ Const lut = cell->getParam("\\LUT");
+ int count = 1;
+
+ if (GetSize(sig_a) == 1)
+ {
+ cell->module->addMuxGate(NEW_ID, lut[0], lut[1], sig_a, sig_y);
+ }
+ else
+ {
+ SigSpec sig_a_hi = sig_a[GetSize(sig_a)-1];
+ SigSpec sig_a_lo = sig_a.extract(0, GetSize(sig_a)-1);
+ SigSpec sig_y1 = cell->module->addWire(NEW_ID);
+ SigSpec sig_y2 = cell->module->addWire(NEW_ID);
+
+ Const lut1 = lut.extract(0, GetSize(lut)/2);
+ Const lut2 = lut.extract(GetSize(lut)/2, GetSize(lut)/2);
+
+ count += lut2mux(cell->module->addLut(NEW_ID, sig_a_lo, sig_y1, lut1));
+ count += lut2mux(cell->module->addLut(NEW_ID, sig_a_lo, sig_y2, lut2));
+
+ cell->module->addMuxGate(NEW_ID, sig_y1, sig_y2, sig_a_hi, sig_y);
+ }
+
+ cell->module->remove(cell);
+ return count;
+}
+
+struct Lut2muxPass : public Pass {
+ Lut2muxPass() : Pass("lut2mux", "convert $lut to $_MUX_") { }
+ virtual void help()
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" lut2mux [options] [selection]\n");
+ log("\n");
+ log("This pass converts $lut cells to $_MUX_ gates.\n");
+ log("\n");
+ }
+ virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+ {
+ log_header("Executing LUT2MUX pass (mapping to constant drivers).\n");
+
+ size_t argidx;
+ for (argidx = 1; argidx < args.size(); argidx++)
+ {
+ // if (args[argidx] == "-v") {
+ // continue;
+ // }
+ break;
+ }
+ extra_args(args, argidx, design);
+
+ for (auto module : design->selected_modules())
+ for (auto cell : module->selected_cells()) {
+ if (cell->type == "$lut") {
+ IdString cell_name = cell->name;
+ int count = lut2mux(cell);
+ log("Converted %s.%s to %d MUX cells.\n", log_id(module), log_id(cell_name), count);
+ }
+ }
+ }
+} Lut2muxPass;
+
+PRIVATE_NAMESPACE_END