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authorClifford Wolf <clifford@clifford.at>2014-09-08 12:15:39 +0200
committerClifford Wolf <clifford@clifford.at>2014-09-08 12:15:39 +0200
commitd46bac330520f91ee5bf8027abe98a8f9389f696 (patch)
treed1b87a2409d082fa281d2c9ea100e94c69a43912 /passes/techmap/maccmap.cc
parent1a88e47396305bd6b5ee2a7a91a1d014ebd37c10 (diff)
Added "$fa" cell type
Diffstat (limited to 'passes/techmap/maccmap.cc')
-rw-r--r--passes/techmap/maccmap.cc22
1 files changed, 16 insertions, 6 deletions
diff --git a/passes/techmap/maccmap.cc b/passes/techmap/maccmap.cc
index a9c223fa..c2dc9aa8 100644
--- a/passes/techmap/maccmap.cc
+++ b/passes/techmap/maccmap.cc
@@ -106,12 +106,20 @@ struct MaccmapWorker
in2 = in2.extract(start_index, stop_index-start_index);
in3 = in3.extract(start_index, stop_index-start_index);
- RTLIL::SigSpec t1 = module->Xor(NEW_ID, in1, in2);
- out1 = {out_zeros_msb, module->Xor(NEW_ID, t1, in3), out_zeros_lsb};
-
- RTLIL::SigSpec t2 = module->And(NEW_ID, in1, in2);
- RTLIL::SigSpec t3 = module->And(NEW_ID, in3, t1);
- out2 = {out_zeros_msb, module->Or(NEW_ID, t2, t3), out_zeros_lsb};
+ int width = SIZE(in1);
+ RTLIL::Wire *w1 = module->addWire(NEW_ID, width);
+ RTLIL::Wire *w2 = module->addWire(NEW_ID, width);
+
+ RTLIL::Cell *cell = module->addCell(NEW_ID, "$fa");
+ cell->setParam("\\WIDTH", width);
+ cell->setPort("\\A", in1);
+ cell->setPort("\\B", in2);
+ cell->setPort("\\C", in3);
+ cell->setPort("\\Y", w1);
+ cell->setPort("\\X", w2);
+
+ out1 = {out_zeros_msb, w1, out_zeros_lsb};
+ out2 = {out_zeros_msb, w2, out_zeros_lsb};
}
}
@@ -198,6 +206,8 @@ struct MaccmapWorker
summands.swap(new_summands);
}
+ log_assert(tree_sum_bits.empty());
+
return module->Add(NEW_ID, summands.front(), summands.back());
}
};