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authorRuben Undheim <ruben.undheim@gmail.com>2016-11-03 23:18:00 +0100
committerRuben Undheim <ruben.undheim@gmail.com>2016-11-03 23:18:00 +0100
commitfefe0fc0430f4f173a25e674708aa0f4f0854b31 (patch)
treeadb13b830212c269d58031f900d652f29013d2d7 /passes/techmap/techmap.cc
parent4f096fe65b77435daba019248273e547fa18d167 (diff)
Imported yosys 0.7
Diffstat (limited to 'passes/techmap/techmap.cc')
-rw-r--r--passes/techmap/techmap.cc9
1 files changed, 8 insertions, 1 deletions
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index b2cc492b..6784f48c 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -345,6 +345,12 @@ struct TechmapWorker
c->setParam("\\MEMID", Const(memory_renames[memid].str()));
}
+ if (c->type == "$mem") {
+ string memid = c->getParam("\\MEMID").decode_string();
+ apply_prefix(cell->name.str(), memid);
+ c->setParam("\\MEMID", Const(memid));
+ }
+
if (c->attributes.count("\\src"))
c->add_strpool_attribute("\\src", extra_src_attrs);
}
@@ -1164,8 +1170,9 @@ struct FlattenPass : public Pass {
worker.flatten_do_list.erase(mod->name);
}
} else {
- for (auto mod : vector<Module*>(design->modules()))
+ for (auto mod : vector<Module*>(design->modules())) {
while (worker.techmap_module(design, mod, design, handled_cells, celltypeMap, false)) { }
+ }
}
log("No more expansions possible.\n");