Import more std:: stuff into Yosys namespace

7 files changed, 12 insertions, 12 deletions

diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index 64586927..70677988 100644
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -1399,7 +1399,7 @@ struct AbcPass : public Pass {
 				std::set<RTLIL::Cell*> expand_queue_up, next_expand_queue_up;
 				std::set<RTLIL::Cell*> expand_queue_down, next_expand_queue_down;
 
-				typedef std::tuple<bool, RTLIL::SigSpec, bool, RTLIL::SigSpec> clkdomain_t;
+				typedef tuple<bool, RTLIL::SigSpec, bool, RTLIL::SigSpec> clkdomain_t;
 				std::map<clkdomain_t, std::vector<RTLIL::Cell*>> assigned_cells;
 				std::map<RTLIL::Cell*, clkdomain_t> assigned_cells_reverse;
 
diff --git a/passes/techmap/alumacc.cc b/passes/techmap/alumacc.cc
index 90563c86..3c7ff4b9 100644
--- a/passes/techmap/alumacc.cc
+++ b/passes/techmap/alumacc.cc
@@ -40,7 +40,7 @@ struct AlumaccWorker
 	{
 		std::vector<RTLIL::Cell*> cells;
 		RTLIL::SigSpec a, b, c, y;
-		std::vector<std::tuple<bool, bool, bool, bool, RTLIL::SigSpec>> cmp;
+		std::vector<tuple<bool, bool, bool, bool, RTLIL::SigSpec>> cmp;
 		bool is_signed, invert_b;
 
 		RTLIL::Cell *alu_cell;
@@ -138,7 +138,7 @@ struct AlumaccWorker
 			n->users = 0;
 
 			for (auto bit : n->y)
-				n->users = std::max(n->users, bit_users.at(bit) - 1);
+				n->users = max(n->users, bit_users.at(bit) - 1);
 
 			if (cell->type.in("$pos", "$neg"))
 			{
@@ -409,7 +409,7 @@ struct AlumaccWorker
 				n->a = A;
 				n->b = B;
 				n->c = RTLIL::S1;
-				n->y = module->addWire(NEW_ID, std::max(GetSize(A), GetSize(B)));
+				n->y = module->addWire(NEW_ID, max(GetSize(A), GetSize(B)));
 				n->is_signed = is_signed;
 				n->invert_b = true;
 				sig_alu[RTLIL::SigSig(A, B)].insert(n);
diff --git a/passes/techmap/dffinit.cc b/passes/techmap/dffinit.cc
index 84770ff3..6a80f043 100644
--- a/passes/techmap/dffinit.cc
+++ b/passes/techmap/dffinit.cc
@@ -68,7 +68,7 @@ struct DffinitPass : public Pass {
 			for (auto wire : module->selected_wires()) {
 				if (wire->attributes.count("\\init")) {
 					Const value = wire->attributes.at("\\init");
-					for (int i = 0; i < std::min(GetSize(value), GetSize(wire)); i++)
+					for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++)
 						init_bits[sigmap(SigBit(wire, i))] = value[i];
 				}
 				if (wire->port_output)
@@ -116,7 +116,7 @@ struct DffinitPass : public Pass {
 				if (wire->attributes.count("\\init")) {
 					Const &value = wire->attributes.at("\\init");
 					bool do_cleanup = true;
-					for (int i = 0; i < std::min(GetSize(value), GetSize(wire)); i++) {
+					for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++) {
 						SigBit bit = sigmap(SigBit(wire, i));
 						if (cleanup_bits.count(bit) || !used_bits.count(bit))
 							value[i] = State::Sx;
diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index d9ec4bc6..fc73177c 100644
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -130,7 +130,7 @@ public:
 				RTLIL::SigSpec needleSig = conn.second;
 				RTLIL::SigSpec haystackSig = haystackCell->getPort(portMapping.at(conn.first.str()));
 
-				for (int i = 0; i < std::min(needleSig.size(), haystackSig.size()); i++) {
+				for (int i = 0; i < min(needleSig.size(), haystackSig.size()); i++) {
 					RTLIL::Wire *needleWire = needleSig[i].wire, *haystackWire = haystackSig[i].wire;
 					if (needleWire != lastNeedleWire || haystackWire != lastHaystackWire)
 						if (!compareAttributes(wire_attr, needleWire ? needleWire->attributes : emptyAttr, haystackWire ? haystackWire->attributes : emptyAttr))
diff --git a/passes/techmap/maccmap.cc b/passes/techmap/maccmap.cc
index dad1c06a..d5b8fe80 100644
--- a/passes/techmap/maccmap.cc
+++ b/passes/techmap/maccmap.cc
@@ -134,7 +134,7 @@ struct MaccmapWorker
 		}
 		return retval;
 	#else
-		return std::max(n - 1, 0);
+		return max(n - 1, 0);
 	#endif
 	}
 
diff --git a/passes/techmap/muxcover.cc b/passes/techmap/muxcover.cc
index b250c568..514c3365 100644
--- a/passes/techmap/muxcover.cc
+++ b/passes/techmap/muxcover.cc
@@ -49,8 +49,8 @@ struct MuxcoverWorker
 
 	vector<tree_t> tree_list;
 
-	dict<std::tuple<SigBit, SigBit, SigBit>, std::tuple<SigBit, pool<SigBit>, bool>> decode_mux_cache;
-	dict<SigBit, std::tuple<SigBit, SigBit, SigBit>> decode_mux_reverse_cache;
+	dict<tuple<SigBit, SigBit, SigBit>, tuple<SigBit, pool<SigBit>, bool>> decode_mux_cache;
+	dict<SigBit, tuple<SigBit, SigBit, SigBit>> decode_mux_reverse_cache;
 	int decode_mux_counter;
 
 	bool use_mux4;
@@ -142,7 +142,7 @@ struct MuxcoverWorker
 		if (A == B)
 			return 0;
 
-		std::tuple<SigBit, SigBit, SigBit> key(A, B, sel);
+		tuple<SigBit, SigBit, SigBit> key(A, B, sel);
 		if (decode_mux_cache.count(key) == 0) {
 			auto &entry = decode_mux_cache[key];
 			std::get<0>(entry) = module->addWire(NEW_ID);
diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc
index 0fb5b374..956cd48f 100644
--- a/passes/techmap/simplemap.cc
+++ b/passes/techmap/simplemap.cc
@@ -247,7 +247,7 @@ void simplemap_eqne(RTLIL::Module *module, RTLIL::Cell *cell)
 	bool is_signed = cell->parameters.at("\\A_SIGNED").as_bool();
 	bool is_ne = cell->type == "$ne" || cell->type == "$nex";
 
-	RTLIL::SigSpec xor_out = module->addWire(NEW_ID, std::max(GetSize(sig_a), GetSize(sig_b)));
+	RTLIL::SigSpec xor_out = module->addWire(NEW_ID, max(GetSize(sig_a), GetSize(sig_b)));
 	RTLIL::Cell *xor_cell = module->addXor(NEW_ID, sig_a, sig_b, xor_out, is_signed);
 	xor_cell->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
 	simplemap_bitop(module, xor_cell);