equiv_purge bugfix, using SigChunk in Yosys namespace

2 files changed, 2 insertions, 2 deletions

diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index 68a7fc1f..d9ec4bc6 100644
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -737,7 +737,7 @@ struct ExtractPass : public Pass {
 					RTLIL::Cell *newCell = newMod->addCell(cell->name, cell->type);
 					newCell->parameters = cell->parameters;
 					for (auto &conn : cell->connections()) {
-						std::vector<RTLIL::SigChunk> chunks = sigmap(conn.second);
+						std::vector<SigChunk> chunks = sigmap(conn.second);
 						for (auto &chunk : chunks)
 							if (chunk.wire != NULL)
 								chunk.wire = newMod->wires_.at(chunk.wire->name);
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 592710ed..19b2bda9 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -49,7 +49,7 @@ void apply_prefix(std::string prefix, std::string &id)
 
 void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module *module)
 {
-	std::vector<RTLIL::SigChunk> chunks = sig;
+	vector<SigChunk> chunks = sig;
 	for (auto &chunk : chunks)
 		if (chunk.wire != NULL) {
 			std::string wire_name = chunk.wire->name.str();