Spell check (by Larry Doolittle)

4 files changed, 14 insertions, 14 deletions

diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index c19593f0..d1e629b5 100644
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -1158,7 +1158,7 @@ struct AbcPass : public Pass {
 		log("        use the specified ABC script file instead of the default script.\n");
 		log("\n");
 		log("        if <file> starts with a plus sign (+), then the rest of the filename\n");
-		log("        string is interprated as the command string to be passed to ABC. the\n");
+		log("        string is interpreted as the command string to be passed to ABC. The\n");
 		log("        leading plus sign is removed and all commas (,) in the string are\n");
 		log("        replaced with blanks before the string is passed to ABC.\n");
 		log("\n");
@@ -1235,7 +1235,7 @@ struct AbcPass : public Pass {
 		log("\n");
 		log("    -keepff\n");
 		log("        set the \"keep\" attribute on flip-flop output wires. (and thus preserve\n");
-		log("        them, for example for equivialence checking.)\n");
+		log("        them, for example for equivalence checking.)\n");
 		log("\n");
 		log("    -nocleanup\n");
 		log("        when this option is used, the temporary files created by this pass\n");
diff --git a/passes/techmap/dff2dffe.cc b/passes/techmap/dff2dffe.cc
index e587f827..51bfaade 100644
--- a/passes/techmap/dff2dffe.cc
+++ b/passes/techmap/dff2dffe.cc
@@ -273,7 +273,7 @@ struct Dff2dffePass : public Pass {
 		log("        <external_gate_type> is the cell type name for a cell with an\n");
 		log("        identical interface to the <internal_gate_type>, except it\n");
 		log("        also has an high-active enable port 'E'.\n");
-		log("          Usually <external_gate_type> is an intemediate cell type\n");
+		log("          Usually <external_gate_type> is an intermediate cell type\n");
 		log("        that is then translated to the final type using 'techmap'.\n");
 		log("\n");
 		log("    -direct-match <pattern>\n");
diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index b670083b..3c24524d 100644
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -390,11 +390,11 @@ struct ExtractPass : public Pass {
 		log("        match. This option can be used multiple times.\n");
 		log("\n");
 		log("    -swap <needle_type> <port1>,<port2>[,...]\n");
-		log("        Register a set of swapable ports for a needle cell type.\n");
+		log("        Register a set of swappable ports for a needle cell type.\n");
 		log("        This option can be used multiple times.\n");
 		log("\n");
 		log("    -perm <needle_type> <port1>,<port2>[,...] <portA>,<portB>[,...]\n");
-		log("        Register a valid permutation of swapable ports for a needle\n");
+		log("        Register a valid permutation of swappable ports for a needle\n");
 		log("        cell type. This option can be used multiple times.\n");
 		log("\n");
 		log("    -cell_attr <attribute_name>\n");
@@ -409,7 +409,7 @@ struct ExtractPass : public Pass {
 		log("    -ignore_param <cell_type> <parameter_name>\n");
 		log("        Do not use this parameter when matching cells.\n");
 		log("\n");
-		log("This pass does not operate on modules with uprocessed processes in it.\n");
+		log("This pass does not operate on modules with unprocessed processes in it.\n");
 		log("(I.e. the 'proc' pass should be used first to convert processes to netlists.)\n");
 		log("\n");
 		log("This pass can also be used for mining for frequent subcircuits. In this mode\n");
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 1a16b6f4..8ba02831 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -850,7 +850,7 @@ struct TechmapPass : public Pass {
 		log("    techmap [-map filename] [selection]\n");
 		log("\n");
 		log("This pass implements a very simple technology mapper that replaces cells in\n");
-		log("the design with implementations given in form of a verilog or ilang source\n");
+		log("the design with implementations given in form of a Verilog or ilang source\n");
 		log("file.\n");
 		log("\n");
 		log("    -map filename\n");
@@ -871,7 +871,7 @@ struct TechmapPass : public Pass {
 		log("\n");
 		log("    -recursive\n");
 		log("        instead of the iterative breadth-first algorithm use a recursive\n");
-		log("        depth-first algorithm. both methods should yield equivialent results,\n");
+		log("        depth-first algorithm. both methods should yield equivalent results,\n");
 		log("        but may differ in performance.\n");
 		log("\n");
 		log("    -autoproc\n");
@@ -883,8 +883,8 @@ struct TechmapPass : public Pass {
 		log("        as final cell types by this mode.\n");
 		log("\n");
 		log("    -D <define>, -I <incdir>\n");
-		log("        this options are passed as-is to the verilog frontend for loading the\n");
-		log("        map file. Note that the verilog frontend is also called with the\n");
+		log("        this options are passed as-is to the Verilog frontend for loading the\n");
+		log("        map file. Note that the Verilog frontend is also called with the\n");
 		log("        '-ignore_redef' option set.\n");
 		log("\n");
 		log("When a module in the map file has the 'techmap_celltype' attribute set, it will\n");
@@ -930,7 +930,7 @@ struct TechmapPass : public Pass {
 		log("        of constant inputs and shorted inputs at this point and import the\n");
 		log("        constant and connected bits into the map module. All further commands\n");
 		log("        are executed in this copy. This is a very convenient way of creating\n");
-		log("        optimizied specializations of techmap modules without using the special\n");
+		log("        optimized specializations of techmap modules without using the special\n");
 		log("        parameters described below.\n");
 		log("\n");
 		log("        A _TECHMAP_DO_* command may start with the special token 'RECURSION; '.\n");
@@ -966,12 +966,12 @@ struct TechmapPass : public Pass {
 		log("constant value.\n");
 		log("\n");
 		log("A cell with the name _TECHMAP_REPLACE_ in the map file will inherit the name\n");
-		log("of the cell that is beeing replaced.\n");
+		log("of the cell that is being replaced.\n");
 		log("\n");
 		log("See 'help extract' for a pass that does the opposite thing.\n");
 		log("\n");
 		log("See 'help flatten' for a pass that does flatten the design (which is\n");
-		log("esentially techmap but using the design itself as map library).\n");
+		log("essentially techmap but using the design itself as map library).\n");
 		log("\n");
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
@@ -1099,7 +1099,7 @@ struct FlattenPass : public Pass {
 		log("    flatten [selection]\n");
 		log("\n");
 		log("This pass flattens the design by replacing cells by their implementation. This\n");
-		log("pass is very simmilar to the 'techmap' pass. The only difference is that this\n");
+		log("pass is very similar to the 'techmap' pass. The only difference is that this\n");
 		log("pass is using the current design as mapping library.\n");
 		log("\n");
 		log("Cells and/or modules with the 'keep_hiearchy' attribute set will not be\n");