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authorRuben Undheim <ruben.undheim@gmail.com>2016-11-03 23:18:00 +0100
committerRuben Undheim <ruben.undheim@gmail.com>2016-11-03 23:18:00 +0100
commitfefe0fc0430f4f173a25e674708aa0f4f0854b31 (patch)
treeadb13b830212c269d58031f900d652f29013d2d7 /passes/techmap
parent4f096fe65b77435daba019248273e547fa18d167 (diff)
Imported yosys 0.7
Diffstat (limited to 'passes/techmap')
-rw-r--r--passes/techmap/Makefile.inc1
-rw-r--r--passes/techmap/attrmap.cc23
-rw-r--r--passes/techmap/attrmvcp.cc2
-rw-r--r--passes/techmap/simplemap.cc20
-rw-r--r--passes/techmap/techmap.cc9
-rw-r--r--passes/techmap/zinit.cc151
6 files changed, 202 insertions, 4 deletions
diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc
index b5024fa9..311a1af9 100644
--- a/passes/techmap/Makefile.inc
+++ b/passes/techmap/Makefile.inc
@@ -31,6 +31,7 @@ OBJS += passes/techmap/deminout.o
OBJS += passes/techmap/insbuf.o
OBJS += passes/techmap/attrmvcp.o
OBJS += passes/techmap/attrmap.o
+OBJS += passes/techmap/zinit.o
endif
GENFILES += passes/techmap/techmap.inc
diff --git a/passes/techmap/attrmap.cc b/passes/techmap/attrmap.cc
index f715b63e..dec81d21 100644
--- a/passes/techmap/attrmap.cc
+++ b/passes/techmap/attrmap.cc
@@ -33,13 +33,32 @@ Const make_value(string &value)
return sig.as_const();
}
+bool string_compare_nocase(const string &str1, const string &str2)
+{
+ if (str1.size() != str2.size())
+ return false;
+
+ for (size_t i = 0; i < str1.size(); i++)
+ {
+ char ch1 = str1[i], ch2 = str2[i];
+ if ('a' <= ch1 && ch1 <= 'z')
+ ch1 -= 'a' - 'A';
+ if ('a' <= ch2 && ch2 <= 'z')
+ ch2 -= 'a' - 'A';
+ if (ch1 != ch2)
+ return false;
+ }
+
+ return true;
+}
+
bool match_name(string &name, IdString &id, bool ignore_case=false)
{
string str1 = RTLIL::escape_id(name);
string str2 = id.str();
if (ignore_case)
- return !strcasecmp(str1.c_str(), str2.c_str());
+ return string_compare_nocase(str1, str2);
return str1 == str2;
}
@@ -49,7 +68,7 @@ bool match_value(string &value, Const &val, bool ignore_case=false)
if (ignore_case && ((val.flags & RTLIL::CONST_FLAG_STRING) != 0) && GetSize(value) && value.front() == '"' && value.back() == '"') {
string str1 = value.substr(1, GetSize(value)-2);
string str2 = val.decode_string();
- return !strcasecmp(str1.c_str(), str2.c_str());
+ return string_compare_nocase(str1, str2);
}
return make_value(value) == val;
diff --git a/passes/techmap/attrmvcp.cc b/passes/techmap/attrmvcp.cc
index 50eaf61d..1537def0 100644
--- a/passes/techmap/attrmvcp.cc
+++ b/passes/techmap/attrmvcp.cc
@@ -93,6 +93,7 @@ struct AttrmvcpPass : public Pass {
for (auto cell : module->selected_cells())
for (auto &conn : cell->connections())
+ {
if (driven_mode) {
if (cell->input(conn.first))
for (auto bit : sigmap(conn.second))
@@ -102,6 +103,7 @@ struct AttrmvcpPass : public Pass {
for (auto bit : sigmap(conn.second))
net2cells[bit].insert(cell);
}
+ }
for (auto wire : module->selected_wires())
{
diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc
index 0fb64734..c6b932bd 100644
--- a/passes/techmap/simplemap.cc
+++ b/passes/techmap/simplemap.cc
@@ -388,6 +388,23 @@ void simplemap_sr(RTLIL::Module *module, RTLIL::Cell *cell)
}
}
+void simplemap_ff(RTLIL::Module *module, RTLIL::Cell *cell)
+{
+ int width = cell->parameters.at("\\WIDTH").as_int();
+
+ RTLIL::SigSpec sig_d = cell->getPort("\\D");
+ RTLIL::SigSpec sig_q = cell->getPort("\\Q");
+
+ std::string gate_type = "$_FF_";
+
+ for (int i = 0; i < width; i++) {
+ RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
+ gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
+ gate->setPort("\\D", sig_d[i]);
+ gate->setPort("\\Q", sig_q[i]);
+ }
+}
+
void simplemap_dff(RTLIL::Module *module, RTLIL::Cell *cell)
{
int width = cell->parameters.at("\\WIDTH").as_int();
@@ -532,6 +549,7 @@ void simplemap_get_mappers(std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTL
mappers["$slice"] = simplemap_slice;
mappers["$concat"] = simplemap_concat;
mappers["$sr"] = simplemap_sr;
+ mappers["$ff"] = simplemap_ff;
mappers["$dff"] = simplemap_dff;
mappers["$dffe"] = simplemap_dffe;
mappers["$dffsr"] = simplemap_dffsr;
@@ -569,7 +587,7 @@ struct SimplemapPass : public Pass {
log(" $not, $pos, $and, $or, $xor, $xnor\n");
log(" $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor, $reduce_bool\n");
log(" $logic_not, $logic_and, $logic_or, $mux, $tribuf\n");
- log(" $sr, $dff, $dffsr, $adff, $dlatch\n");
+ log(" $sr, $ff, $dff, $dffsr, $adff, $dlatch\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index b2cc492b..6784f48c 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -345,6 +345,12 @@ struct TechmapWorker
c->setParam("\\MEMID", Const(memory_renames[memid].str()));
}
+ if (c->type == "$mem") {
+ string memid = c->getParam("\\MEMID").decode_string();
+ apply_prefix(cell->name.str(), memid);
+ c->setParam("\\MEMID", Const(memid));
+ }
+
if (c->attributes.count("\\src"))
c->add_strpool_attribute("\\src", extra_src_attrs);
}
@@ -1164,8 +1170,9 @@ struct FlattenPass : public Pass {
worker.flatten_do_list.erase(mod->name);
}
} else {
- for (auto mod : vector<Module*>(design->modules()))
+ for (auto mod : vector<Module*>(design->modules())) {
while (worker.techmap_module(design, mod, design, handled_cells, celltypeMap, false)) { }
+ }
}
log("No more expansions possible.\n");
diff --git a/passes/techmap/zinit.cc b/passes/techmap/zinit.cc
new file mode 100644
index 00000000..a577e123
--- /dev/null
+++ b/passes/techmap/zinit.cc
@@ -0,0 +1,151 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct ZinitPass : public Pass {
+ ZinitPass() : Pass("zinit", "add inverters so all FF are zero-initialized") { }
+ virtual void help()
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" zinit [options] [selection]\n");
+ log("\n");
+ log("Add inverters as needed to make all FFs zero-initialized.\n");
+ log("\n");
+ log(" -all\n");
+ log(" also add zero initialization to uninitialized FFs\n");
+ log("\n");
+ }
+ virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+ {
+ bool all_mode = false;
+
+ log_header(design, "Executing ZINIT pass (make all FFs zero-initialized).\n");
+
+ size_t argidx;
+ for (argidx = 1; argidx < args.size(); argidx++)
+ {
+ if (args[argidx] == "-singleton") {
+ all_mode = true;
+ continue;
+ }
+ break;
+ }
+ extra_args(args, argidx, design);
+
+ for (auto module : design->selected_modules())
+ {
+ SigMap sigmap(module);
+ dict<SigBit, State> initbits;
+ pool<SigBit> donebits;
+
+ for (auto wire : module->selected_wires())
+ {
+ if (wire->attributes.count("\\init") == 0)
+ continue;
+
+ SigSpec wirebits = sigmap(wire);
+ Const initval = wire->attributes.at("\\init");
+ wire->attributes.erase("\\init");
+
+ for (int i = 0; i < GetSize(wirebits) && i < GetSize(initval); i++)
+ {
+ SigBit bit = wirebits[i];
+ State val = initval[i];
+
+ if (val != State::S0 && val != State::S1 && bit.wire != nullptr)
+ continue;
+
+ if (initbits.count(bit)) {
+ if (initbits.at(bit) != val)
+ log_error("Conflicting init values for signal %s (%s = %s != %s).\n",
+ log_signal(bit), log_signal(SigBit(wire, i)),
+ log_signal(val), log_signal(initbits.at(bit)));
+ continue;
+ }
+
+ initbits[bit] = val;
+ }
+ }
+
+ pool<IdString> dff_types = {
+ "$ff", "$dff", "$dffe", "$dffsr", "$adff",
+ "$_FF_", "$_DFFE_NN_", "$_DFFE_NP_", "$_DFFE_PN_", "$_DFFE_PP_",
+ "$_DFFSR_NNN_", "$_DFFSR_NNP_", "$_DFFSR_NPN_", "$_DFFSR_NPP_",
+ "$_DFFSR_PNN_", "$_DFFSR_PNP_", "$_DFFSR_PPN_", "$_DFFSR_PPP_",
+ "$_DFF_N_", "$_DFF_NN0_", "$_DFF_NN1_", "$_DFF_NP0_", "$_DFF_NP1_",
+ "$_DFF_P_", "$_DFF_PN0_", "$_DFF_PN1_", "$_DFF_PP0_", "$_DFF_PP1_"
+ };
+
+ for (auto cell : module->selected_cells())
+ {
+ if (!dff_types.count(cell->type))
+ continue;
+
+ SigSpec sig_d = sigmap(cell->getPort("\\D"));
+ SigSpec sig_q = sigmap(cell->getPort("\\Q"));
+
+ if (GetSize(sig_d) < 1 || GetSize(sig_q) < 1)
+ continue;
+
+ Const initval;
+
+ for (int i = 0; i < GetSize(sig_q); i++) {
+ if (initbits.count(sig_q[i])) {
+ initval.bits.push_back(initbits.at(sig_q[i]));
+ donebits.insert(sig_q[i]);
+ } else
+ initval.bits.push_back(all_mode ? State::S0 : State::Sx);
+ }
+
+ Wire *initwire = module->addWire(NEW_ID, GetSize(initval));
+ initwire->attributes["\\init"] = initval;
+
+ for (int i = 0; i < GetSize(initwire); i++)
+ if (initval.bits.at(i) == State::S1)
+ {
+ sig_d[i] = module->NotGate(NEW_ID, sig_d[i]);
+ module->addNotGate(NEW_ID, SigSpec(initwire, i), sig_q[i]);
+ initwire->attributes["\\init"].bits.at(i) = State::S0;
+ }
+ else
+ {
+ module->connect(sig_q[i], SigSpec(initwire, i));
+ }
+
+ log("FF init value for cell %s (%s): %s = %s\n", log_id(cell), log_id(cell->type),
+ log_signal(sig_q), log_signal(initval));
+
+ cell->setPort("\\D", sig_d);
+ cell->setPort("\\Q", initwire);
+ }
+
+ for (auto &it : initbits)
+ if (donebits.count(it.first) == 0)
+ log_error("Failed to handle init bit %s = %s.\n", log_signal(it.first), log_signal(it.second));
+ }
+ }
+} ZinitPass;
+
+PRIVATE_NAMESPACE_END