diff options
| author | Clifford Wolf <clifford@clifford.at> | 2015-10-25 19:30:49 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-10-25 19:30:49 +0100 |
| commit | 207736b4ee0363ff6714071e64024965916eafc2 (patch) | |
| tree | 31092cfab4323500bc491d8b59deee9e297730d0 /passes/tests/test_cell.cc | |
| parent | da923c198e770806a4abb749acc75fa337247920 (diff) | |
Import more std:: stuff into Yosys namespace
Diffstat (limited to 'passes/tests/test_cell.cc')
| -rw-r--r-- | passes/tests/test_cell.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index fd5a32e4..a8fcac9b 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -256,7 +256,7 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, case 2: n = xorshift32(GetSize(sig)); m = xorshift32(GetSize(sig)); - for (int i = std::min(n, m); i < std::max(n, m); i++) + for (int i = min(n, m); i < max(n, m); i++) sig[i] = xorshift32(2) == 1 ? RTLIL::S1 : RTLIL::S0; break; } |