Replaced ezDefaultSAT with ezSatPtr

2 files changed, 17 insertions, 17 deletions

diff --git a/passes/tests/test_abcloop.cc b/passes/tests/test_abcloop.cc
index 753fa7bf..09cb4195 100644
--- a/passes/tests/test_abcloop.cc
+++ b/passes/tests/test_abcloop.cc
@@ -127,9 +127,9 @@ static void test_abcloop()
 		module->fixup_ports();
 		Pass::call(design, "clean");
 
-		ezDefaultSAT ez;
+		ezSatPtr ez;
 		SigMap sigmap(module);
-		SatGen satgen(&ez, &sigmap);
+		SatGen satgen(ez.get(), &sigmap);
 
 		for (auto c : module->cells()) {
 			bool ok YS_ATTRIBUTE(unused) = satgen.importCell(c);
@@ -137,7 +137,7 @@ static void test_abcloop()
 		}
 
 		std::vector<int> in_vec = satgen.importSigSpec(in_sig);
-		std::vector<int> inverse_in_vec = ez.vec_not(in_vec);
+		std::vector<int> inverse_in_vec = ez->vec_not(in_vec);
 
 		std::vector<int> out_vec = satgen.importSigSpec(out_sig);
 
@@ -148,7 +148,7 @@ static void test_abcloop()
 				assumptions.push_back((i & (1 << j)) ? in_vec.at(j) : inverse_in_vec.at(j));
 
 			std::vector<bool> results;
-			if (!ez.solve(out_vec, results, assumptions)) {
+			if (!ez->solve(out_vec, results, assumptions)) {
 				log("No stable solution for input %d found -> recreate module.\n", i);
 				goto recreate_module;
 			}
@@ -156,10 +156,10 @@ static void test_abcloop()
 			for (int j = 0; j < 4; j++)
 				truthtab[i][j] = results[j];
 
-			assumptions.push_back(ez.vec_ne(out_vec, ez.vec_const(results)));
+			assumptions.push_back(ez->vec_ne(out_vec, ez->vec_const(results)));
 
 			std::vector<bool> results2;
-			if (ez.solve(out_vec, results2, assumptions)) {
+			if (ez->solve(out_vec, results2, assumptions)) {
 				log("Two stable solutions for input %d found -> recreate module.\n", i);
 				goto recreate_module;
 			}
@@ -177,9 +177,9 @@ static void test_abcloop()
 	log("\n");
 	log("Pre- and post-abc truth table:\n");
 
-	ezDefaultSAT ez;
+	ezSatPtr ez;
 	SigMap sigmap(module);
-	SatGen satgen(&ez, &sigmap);
+	SatGen satgen(ez.get(), &sigmap);
 
 	for (auto c : module->cells()) {
 		bool ok YS_ATTRIBUTE(unused) = satgen.importCell(c);
@@ -187,7 +187,7 @@ static void test_abcloop()
 	}
 
 	std::vector<int> in_vec = satgen.importSigSpec(in_sig);
-	std::vector<int> inverse_in_vec = ez.vec_not(in_vec);
+	std::vector<int> inverse_in_vec = ez->vec_not(in_vec);
 
 	std::vector<int> out_vec = satgen.importSigSpec(out_sig);
 
@@ -204,7 +204,7 @@ static void test_abcloop()
 			truthtab2[i][j] = truthtab[i][j];
 
 		std::vector<bool> results;
-		if (!ez.solve(out_vec, results, assumptions)) {
+		if (!ez->solve(out_vec, results, assumptions)) {
 			log("No stable solution for input %d found.\n", i);
 			found_error = true;
 			continue;
@@ -213,10 +213,10 @@ static void test_abcloop()
 		for (int j = 0; j < 4; j++)
 			truthtab2[i][j] = results[j];
 
-		assumptions.push_back(ez.vec_ne(out_vec, ez.vec_const(results)));
+		assumptions.push_back(ez->vec_ne(out_vec, ez->vec_const(results)));
 
 		std::vector<bool> results2;
-		if (ez.solve(out_vec, results2, assumptions)) {
+		if (ez->solve(out_vec, results2, assumptions)) {
 			log("Two stable solutions for input %d found -> recreate module.\n", i);
 			found_error = true;
 		}
diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc
index ea2ab1e6..268f2559 100644
--- a/passes/tests/test_cell.cc
+++ b/passes/tests/test_cell.cc
@@ -278,10 +278,10 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std::
 	RTLIL::Module *gate_mod = design->module("\\gate");
 	ConstEval gold_ce(gold_mod), gate_ce(gate_mod);
 
-	ezDefaultSAT ez1, ez2;
+	ezSatPtr ez1, ez2;
 	SigMap sigmap(gold_mod);
-	SatGen satgen1(&ez1, &sigmap);
-	SatGen satgen2(&ez2, &sigmap);
+	SatGen satgen1(ez1.get(), &sigmap);
+	SatGen satgen2(ez2.get(), &sigmap);
 	satgen2.model_undef = true;
 
 	if (!nosat)
@@ -433,7 +433,7 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std::
 			std::vector<int> sat1_model = satgen1.importSigSpec(out_sig);
 			std::vector<bool> sat1_model_value;
 
-			if (!ez1.solve(sat1_model, sat1_model_value, ez1.vec_eq(sat1_in_sig, sat1_in_val)))
+			if (!ez1->solve(sat1_model, sat1_model_value, ez1->vec_eq(sat1_in_sig, sat1_in_val)))
 				log_error("Evaluating sat model 1 (no undef modeling) failed!\n");
 
 			if (verbose) {
@@ -468,7 +468,7 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std::
 
 			std::vector<bool> sat2_model_value;
 
-			if (!ez2.solve(sat2_model, sat2_model_value, ez2.vec_eq(sat2_in_def_sig, sat2_in_def_val), ez2.vec_eq(sat2_in_undef_sig, sat2_in_undef_val)))
+			if (!ez2->solve(sat2_model, sat2_model_value, ez2->vec_eq(sat2_in_def_sig, sat2_in_def_val), ez2->vec_eq(sat2_in_undef_sig, sat2_in_undef_val)))
 				log_error("Evaluating sat model 2 (undef modeling) failed!\n");
 
 			if (verbose) {