Improved TopoSort determinism

3 files changed, 7 insertions, 5 deletions

diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc
index e00d5e3b..1e59f18c 100644
--- a/passes/opt/opt_const.cc
+++ b/passes/opt/opt_const.cc
@@ -198,7 +198,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 	SigMap assign_map(module);
 	std::map<RTLIL::SigSpec, RTLIL::SigSpec> invert_map;
 
-	TopoSort<RTLIL::Cell*> cells;
+	TopoSort<RTLIL::Cell*, RTLIL::IdString::compare_ptr_by_name<RTLIL::Cell>> cells;
 	std::map<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_inbit;
 	std::map<RTLIL::SigBit, std::set<RTLIL::Cell*>> outbit_to_cell;
 
diff --git a/passes/opt/share.cc b/passes/opt/share.cc
index 2496f15d..cb751055 100644
--- a/passes/opt/share.cc
+++ b/passes/opt/share.cc
@@ -27,6 +27,8 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
+typedef RTLIL::IdString::compare_ptr_by_name<RTLIL::Cell> cell_ptr_cmp;
+
 struct ShareWorkerConfig
 {
 	int limit;
@@ -52,8 +54,8 @@ struct ShareWorker
 	std::set<RTLIL::Cell*> recursion_state;
 
 	SigMap topo_sigmap;
-	std::map<RTLIL::Cell*, std::set<RTLIL::Cell*>> topo_cell_drivers;
-	std::map<RTLIL::SigBit, std::set<RTLIL::Cell*>> topo_bit_drivers;
+	std::map<RTLIL::Cell*, std::set<RTLIL::Cell*, cell_ptr_cmp>, cell_ptr_cmp> topo_cell_drivers;
+	std::map<RTLIL::SigBit, std::set<RTLIL::Cell*, cell_ptr_cmp>> topo_bit_drivers;
 
 	std::vector<std::pair<RTLIL::SigBit, RTLIL::SigBit>> exclusive_ctrls;
 
@@ -937,7 +939,7 @@ struct ShareWorker
 		ct.setup_internals();
 		ct.setup_stdcells();
 
-		TopoSort<RTLIL::Cell*> toposort;
+		TopoSort<RTLIL::Cell*, cell_ptr_cmp> toposort;
 		toposort.analyze_loops = false;
 
 		topo_sigmap.set(module);
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 73da6ce1..e109c5b5 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -281,7 +281,7 @@ struct TechmapWorker
 
 		SigMap sigmap(module);
 
-		TopoSort<RTLIL::Cell*> cells;
+		TopoSort<RTLIL::Cell*, RTLIL::IdString::compare_ptr_by_name<RTLIL::Cell>> cells;
 		std::map<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_inbit;
 		std::map<RTLIL::SigBit, std::set<RTLIL::Cell*>> outbit_to_cell;