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authorClifford Wolf <clifford@clifford.at>2014-09-14 14:49:53 +0200
committerClifford Wolf <clifford@clifford.at>2014-09-14 14:49:53 +0200
commit014bb34e0ecd058545fafbf1dbb0ba5064714c1d (patch)
tree3d8e48410456a0347685ebc6926514e1523a3294 /passes
parent124e759280fecf9e8698b7e09c5d9e87d8fb3f96 (diff)
Various fixes/cleanups in alumacc and maccmap
Diffstat (limited to 'passes')
-rw-r--r--passes/techmap/alumacc.cc1
-rw-r--r--passes/techmap/maccmap.cc12
2 files changed, 11 insertions, 2 deletions
diff --git a/passes/techmap/alumacc.cc b/passes/techmap/alumacc.cc
index d6ee9e66..3fddcef1 100644
--- a/passes/techmap/alumacc.cc
+++ b/passes/techmap/alumacc.cc
@@ -443,7 +443,6 @@ struct AlumaccWorker
n->alu_cell->setPort("\\X", module->addWire(NEW_ID, SIZE(n->y)));
n->alu_cell->setPort("\\CO", module->addWire(NEW_ID, SIZE(n->y)));
n->alu_cell->fixup_parameters(n->is_signed, n->is_signed);
- log_cell(n->alu_cell);
for (auto &it : n->cmp)
{
diff --git a/passes/techmap/maccmap.cc b/passes/techmap/maccmap.cc
index c2dc9aa8..e17231cb 100644
--- a/passes/techmap/maccmap.cc
+++ b/passes/techmap/maccmap.cc
@@ -208,7 +208,17 @@ struct MaccmapWorker
log_assert(tree_sum_bits.empty());
- return module->Add(NEW_ID, summands.front(), summands.back());
+ RTLIL::Cell *c = module->addCell(NEW_ID, "$alu");
+ c->setPort("\\A", summands.front());
+ c->setPort("\\B", summands.back());
+ c->setPort("\\CI", RTLIL::S0);
+ c->setPort("\\BI", RTLIL::S0);
+ c->setPort("\\Y", module->addWire(NEW_ID, width));
+ c->setPort("\\X", module->addWire(NEW_ID, width));
+ c->setPort("\\CO", module->addWire(NEW_ID, width));
+ c->fixup_parameters();
+
+ return c->getPort("\\Y");
}
};