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authorClifford Wolf <clifford@clifford.at>2013-08-09 12:42:32 +0200
committerClifford Wolf <clifford@clifford.at>2013-08-09 12:42:32 +0200
commit05483619f0b776eda2f96ca7a9bfb8cdc3732a0e (patch)
treedf893fc9929cc54f684f9975834220743199d93e /passes
parentd97782b848bf5da4529e5b732b1ad06177539a93 (diff)
Some fixes to improve determinism
Diffstat (limited to 'passes')
-rw-r--r--passes/fsm/fsm_expand.cc8
-rw-r--r--passes/fsm/fsm_extract.cc51
-rw-r--r--passes/opt/opt_clean.cc4
3 files changed, 33 insertions, 30 deletions
diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc
index ae1f4c16..5756b10c 100644
--- a/passes/fsm/fsm_expand.cc
+++ b/passes/fsm/fsm_expand.cc
@@ -30,12 +30,12 @@ struct FsmExpand
RTLIL::Module *module;
RTLIL::Cell *fsm_cell;
SigMap assign_map;
- SigSet<RTLIL::Cell*> sig2driver, sig2user;
+ SigSet<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> sig2driver, sig2user;
CellTypes ct;
- std::set<RTLIL::Cell*> merged_set;
- std::set<RTLIL::Cell*> current_set;
- std::set<RTLIL::Cell*> no_candidate_set;
+ std::set<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> merged_set;
+ std::set<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> current_set;
+ std::set<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> no_candidate_set;
bool already_optimized;
int limit_transitions;
diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc
index a593c3e6..d077ef4a 100644
--- a/passes/fsm/fsm_extract.cc
+++ b/passes/fsm/fsm_extract.cc
@@ -31,7 +31,7 @@
static RTLIL::Module *module;
static SigMap assign_map;
-typedef std::pair<RTLIL::Cell*,std::string> sig2driver_entry_t;
+typedef std::pair<std::string, std::string> sig2driver_entry_t;
static SigSet<sig2driver_entry_t> sig2driver, sig2trigger;
static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL::SigSpec &ctrl, std::map<RTLIL::Const, int> &states, RTLIL::Const *reset_state = NULL)
@@ -55,14 +55,14 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL
std::set<sig2driver_entry_t> cellport_list;
sig2driver.find(sig, cellport_list);
for (auto &cellport : cellport_list) {
- if ((cellport.first->type != "$mux" && cellport.first->type != "$pmux" && cellport.first->type != "$safe_pmux") || cellport.second != "\\Y") {
- log(" unexpected cell type %s (%s) found in state selection tree.\n",
- cellport.first->type.c_str(), cellport.first->name.c_str());
+ RTLIL::Cell *cell = module->cells.at(cellport.first);
+ if ((cell->type != "$mux" && cell->type != "$pmux" && cell->type != "$safe_pmux") || cellport.second != "\\Y") {
+ log(" unexpected cell type %s (%s) found in state selection tree.\n", cell->type.c_str(), cell->name.c_str());
return false;
}
- RTLIL::SigSpec sig_a = assign_map(cellport.first->connections["\\A"]);
- RTLIL::SigSpec sig_b = assign_map(cellport.first->connections["\\B"]);
- RTLIL::SigSpec sig_s = assign_map(cellport.first->connections["\\S"]);
+ RTLIL::SigSpec sig_a = assign_map(cell->connections["\\A"]);
+ RTLIL::SigSpec sig_b = assign_map(cell->connections["\\B"]);
+ RTLIL::SigSpec sig_s = assign_map(cell->connections["\\S"]);
if (reset_state && RTLIL::SigSpec(*reset_state).is_fully_undef())
do {
if (sig_a.is_fully_def())
@@ -192,17 +192,18 @@ static void extract_fsm(RTLIL::Wire *wire)
std::set<sig2driver_entry_t> cellport_list;
sig2driver.find(dff_out, cellport_list);
for (auto &cellport : cellport_list) {
- if ((cellport.first->type != "$dff" && cellport.first->type != "$adff") || cellport.second != "\\Q")
+ RTLIL::Cell *cell = module->cells.at(cellport.first);
+ if ((cell->type != "$dff" && cell->type != "$adff") || cellport.second != "\\Q")
continue;
- log(" found %s cell for state register: %s\n", cellport.first->type.c_str(), cellport.first->name.c_str());
- RTLIL::SigSpec sig_q = assign_map(cellport.first->connections["\\Q"]);
- RTLIL::SigSpec sig_d = assign_map(cellport.first->connections["\\D"]);
- clk = cellport.first->connections["\\CLK"];
- clk_polarity = cellport.first->parameters["\\CLK_POLARITY"].as_bool();
- if (cellport.first->type == "$adff") {
- arst = cellport.first->connections["\\ARST"];
- arst_polarity = cellport.first->parameters["\\ARST_POLARITY"].as_bool();
- reset_state = cellport.first->parameters["\\ARST_VALUE"];
+ log(" found %s cell for state register: %s\n", cell->type.c_str(), cell->name.c_str());
+ RTLIL::SigSpec sig_q = assign_map(cell->connections["\\Q"]);
+ RTLIL::SigSpec sig_d = assign_map(cell->connections["\\D"]);
+ clk = cell->connections["\\CLK"];
+ clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool();
+ if (cell->type == "$adff") {
+ arst = cell->connections["\\ARST"];
+ arst_polarity = cell->parameters["\\ARST_POLARITY"].as_bool();
+ reset_state = cell->parameters["\\ARST_VALUE"];
}
sig_q.replace(dff_out, sig_d, &dff_in);
break;
@@ -235,9 +236,10 @@ static void extract_fsm(RTLIL::Wire *wire)
cellport_list.clear();
sig2trigger.find(dff_out, cellport_list);
for (auto &cellport : cellport_list) {
- RTLIL::SigSpec sig_a = assign_map(cellport.first->connections["\\A"]);
- RTLIL::SigSpec sig_b = assign_map(cellport.first->connections["\\B"]);
- RTLIL::SigSpec sig_y = assign_map(cellport.first->connections["\\Y"]);
+ RTLIL::Cell *cell = module->cells.at(cellport.first);
+ RTLIL::SigSpec sig_a = assign_map(cell->connections["\\A"]);
+ RTLIL::SigSpec sig_b = assign_map(cell->connections["\\B"]);
+ RTLIL::SigSpec sig_y = assign_map(cell->connections["\\Y"]);
if (cellport.second == "\\A" && !sig_b.is_fully_const())
continue;
if (cellport.second == "\\B" && !sig_a.is_fully_const())
@@ -307,13 +309,14 @@ static void extract_fsm(RTLIL::Wire *wire)
cellport_list.clear();
sig2driver.find(ctrl_out, cellport_list);
for (auto &cellport : cellport_list) {
- RTLIL::SigSpec port_sig = assign_map(cellport.first->connections[cellport.second]);
+ RTLIL::Cell *cell = module->cells.at(cellport.first);
+ RTLIL::SigSpec port_sig = assign_map(cell->connections[cellport.second]);
RTLIL::SigSpec unconn_sig = port_sig.extract(ctrl_out);
RTLIL::Wire *unconn_wire = new RTLIL::Wire;
unconn_wire->name = stringf("$fsm_unconnect$%s$%d", log_signal(unconn_sig), RTLIL::autoidx++);
unconn_wire->width = unconn_sig.width;
module->wires[unconn_wire->name] = unconn_wire;
- port_sig.replace(unconn_sig, RTLIL::SigSpec(unconn_wire), &cellport.first->connections[cellport.second]);
+ port_sig.replace(unconn_sig, RTLIL::SigSpec(unconn_wire), &cell->connections[cellport.second]);
}
}
@@ -361,13 +364,13 @@ struct FsmExtractPass : public Pass {
if (ct.cell_output(cell_it.second->type, conn_it.first)) {
RTLIL::SigSpec sig = conn_it.second;
assign_map.apply(sig);
- sig2driver.insert(sig, sig2driver_entry_t(cell_it.second, conn_it.first));
+ sig2driver.insert(sig, sig2driver_entry_t(cell_it.first, conn_it.first));
}
if (ct.cell_input(cell_it.second->type, conn_it.first) && cell_it.second->connections.count("\\Y") > 0 &&
cell_it.second->connections["\\Y"].width == 1 && (conn_it.first == "\\A" || conn_it.first == "\\B")) {
RTLIL::SigSpec sig = conn_it.second;
assign_map.apply(sig);
- sig2trigger.insert(sig, sig2driver_entry_t(cell_it.second, conn_it.first));
+ sig2trigger.insert(sig, sig2driver_entry_t(cell_it.first, conn_it.first));
}
}
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index dbe1804e..183d6757 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -35,7 +35,7 @@ static int count_rm_cells, count_rm_wires;
static void rmunused_module_cells(RTLIL::Module *module, bool verbose)
{
SigMap assign_map(module);
- std::set<RTLIL::Cell*> queue, unused;
+ std::set<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> queue, unused;
SigSet<RTLIL::Cell*> wire2driver;
for (auto &it : module->cells) {
@@ -66,7 +66,7 @@ static void rmunused_module_cells(RTLIL::Module *module, bool verbose)
while (queue.size() > 0)
{
- std::set<RTLIL::Cell*> new_queue;
+ std::set<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> new_queue;
for (auto cell : queue)
unused.erase(cell);
for (auto cell : queue) {