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authorClifford Wolf <clifford@clifford.at>2015-01-04 11:45:39 +0100
committerClifford Wolf <clifford@clifford.at>2015-01-04 11:45:39 +0100
commit0648e2874c9823e8b4012877b49dfa6eef3d7034 (patch)
tree88a1fb3400db54cc2a0fe3461fe69b4356842b87 /passes
parentf9304e6c10713f713a17f280507f045451863246 (diff)
Fixed pattern matching in "hierarchy -generate"
Diffstat (limited to 'passes')
-rw-r--r--passes/hierarchy/hierarchy.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index 66d66032..58b796a6 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -32,7 +32,7 @@ PRIVATE_NAMESPACE_BEGIN
struct generate_port_decl_t {
bool input, output;
- RTLIL::IdString portname;
+ string portname;
int index;
};
@@ -101,7 +101,7 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes,
for (auto &decl : portdecls)
if (decl.index == 0 && patmatch(decl.portname.c_str(), RTLIL::unescape_id(portname).c_str())) {
generate_port_decl_t d = decl;
- d.portname = portname;
+ d.portname = portname.str();
d.index = *indices.begin();
log_assert(!indices.empty());
indices.erase(d.index);