summaryrefslogtreecommitdiff
path: root/passes
diff options
context:
space:
mode:
authorClifford Wolf <clifford@clifford.at>2015-01-06 14:26:51 +0100
committerClifford Wolf <clifford@clifford.at>2015-01-06 14:26:51 +0100
commit081e1a49f81c298a5c30c4b51241d50ce64f185e (patch)
tree8318a8a68cb21d9ea810bdb2554cfcc4e2b0b625 /passes
parent9c7f47bbd5fc190578054a6d018760c2f2b62c03 (diff)
Towards Xilinx bram support
Diffstat (limited to 'passes')
-rw-r--r--passes/memory/memory_bram.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc
index e7a42f26..fd5db188 100644
--- a/passes/memory/memory_bram.cc
+++ b/passes/memory/memory_bram.cc
@@ -356,7 +356,7 @@ bool replace_cell(Cell *cell, const rules_t::bram_t &bram, const rules_t::match_
for (int i = 0; i < fillbits; i++) {
for (int j = 0; j < wr_ports; j++) {
new_wr_en[j].append(fillbit);
- new_wr_data[j].append(State::Sx);
+ new_wr_data[j].append(State::S0);
}
for (int j = 0; j < rd_ports; j++)
new_rd_data[j].append(State::Sx);