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authorClifford Wolf <clifford@clifford.at>2013-11-07 16:53:28 +0100
committerClifford Wolf <clifford@clifford.at>2013-11-07 16:53:28 +0100
commit0e1661f84e99f1d4a487e7a432b05a6cb2071714 (patch)
tree9862950a7c92069d88e590da6d0a97bf7b7eb95f /passes
parented4bcd52e5d7ab466a4bcd87ae787f1ab7c70fb7 (diff)
Fixed type of sign extension in opt_const $eq/$ne handling
Diffstat (limited to 'passes')
-rw-r--r--passes/opt/opt_const.cc18
1 files changed, 9 insertions, 9 deletions
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc
index b04ed9e7..f20181f1 100644
--- a/passes/opt/opt_const.cc
+++ b/passes/opt/opt_const.cc
@@ -151,8 +151,8 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (cell->parameters["\\A_WIDTH"].as_int() != cell->parameters["\\B_WIDTH"].as_int()) {
int width = std::max(cell->parameters["\\A_WIDTH"].as_int(), cell->parameters["\\B_WIDTH"].as_int());
- a.extend(width, cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool());
- b.extend(width, cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool());
+ a.extend_un0(width, cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool());
+ b.extend_un0(width, cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool());
}
RTLIL::SigSpec new_a, new_b;
@@ -168,6 +168,13 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
new_b.append(b.chunks[i]);
}
+ if (new_a.width == 0) {
+ RTLIL::SigSpec new_y = RTLIL::SigSpec(cell->type == "$eq" ? RTLIL::State::S1 : RTLIL::State::S0);
+ new_y.extend(cell->parameters["\\Y_WIDTH"].as_int(), false);
+ replace_cell(module, cell, "empty", "\\Y", new_y);
+ goto next_cell;
+ }
+
if (new_a.width != a.width) {
new_a.optimize();
new_b.optimize();
@@ -176,13 +183,6 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
cell->parameters["\\A_WIDTH"] = new_a.width;
cell->parameters["\\B_WIDTH"] = new_b.width;
}
-
- if (new_a.width == 0) {
- RTLIL::SigSpec new_y = RTLIL::SigSpec(cell->type == "$eq" ? RTLIL::State::S1 : RTLIL::State::S0);
- new_y.extend(cell->parameters["\\Y_WIDTH"].as_int(), false);
- replace_cell(module, cell, "empty", "\\Y", new_y);
- goto next_cell;
- }
}
if ((cell->type == "$eq" || cell->type == "$ne") && cell->parameters["\\Y_WIDTH"].as_int() == 1 &&