RIP $safe_pmux

8 files changed, 7 insertions, 9 deletions

diff --git a/passes/cmds/wreduce.cc b/passes/cmds/wreduce.cc
index 6723a57f..2269859d 100644
--- a/passes/cmds/wreduce.cc
+++ b/passes/cmds/wreduce.cc
@@ -42,7 +42,7 @@ struct WreduceConfig
 		supported_cell_types << "$shl" << "$shr" << "$sshl" << "$sshr" << "$shift" << "$shiftx";
 		supported_cell_types << "$lt" << "$le" << "$eq" << "$ne" << "$eqx" << "$nex" << "$ge" << "$gt";
 		supported_cell_types << "$add" << "$sub"; // << "$mul" << "$div" << "$mod" << "$pow"
-		supported_cell_types << "$mux" << "$pmux" << "$safe_pmux";
+		supported_cell_types << "$mux" << "$pmux";
 	}
 };
 
@@ -172,7 +172,7 @@ struct WreduceWorker
 		if (!cell->type.in(config->supported_cell_types))
 			return;
 
-		if (cell->type.in("$mux", "$pmux", "$safe_pmux"))
+		if (cell->type.in("$mux", "$pmux"))
 			return run_cell_mux(cell);
 
 
diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc
index 5675dff5..2c846a4c 100644
--- a/passes/fsm/fsm_detect.cc
+++ b/passes/fsm/fsm_detect.cc
@@ -50,7 +50,7 @@ static bool check_state_mux_tree(RTLIL::SigSpec old_sig, RTLIL::SigSpec sig, Sig
 	std::set<sig2driver_entry_t> cellport_list;
 	sig2driver.find(sig, cellport_list);
 	for (auto &cellport : cellport_list) {
-		if ((cellport.first->type != "$mux" && cellport.first->type != "$pmux" && cellport.first->type != "$safe_pmux") || cellport.second != "\\Y")
+		if ((cellport.first->type != "$mux" && cellport.first->type != "$pmux") || cellport.second != "\\Y")
 			return false;
 		RTLIL::SigSpec sig_a = assign_map(cellport.first->getPort("\\A"));
 		RTLIL::SigSpec sig_b = assign_map(cellport.first->getPort("\\B"));
diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc
index 670fae1d..77821326 100644
--- a/passes/fsm/fsm_expand.cc
+++ b/passes/fsm/fsm_expand.cc
@@ -42,7 +42,7 @@ struct FsmExpand
 
 	bool is_cell_merge_candidate(RTLIL::Cell *cell)
 	{
-		if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux")
+		if (cell->type == "$mux" || cell->type == "$pmux")
 			if (cell->getPort("\\A").size() < 2)
 				return true;
 
diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc
index ebe3073d..871478de 100644
--- a/passes/fsm/fsm_extract.cc
+++ b/passes/fsm/fsm_extract.cc
@@ -55,7 +55,7 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL
 	for (auto &cellport : cellport_list)
 	{
 		RTLIL::Cell *cell = module->cells_.at(cellport.first);
-		if ((cell->type != "$mux" && cell->type != "$pmux" && cell->type != "$safe_pmux") || cellport.second != "\\Y") {
+		if ((cell->type != "$mux" && cell->type != "$pmux") || cellport.second != "\\Y") {
 			log("  unexpected cell type %s (%s) found in state selection tree.\n", cell->type.c_str(), cell->name.c_str());
 			return false;
 		}
diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc
index 2660b33d..daa06381 100644
--- a/passes/opt/opt_muxtree.cc
+++ b/passes/opt/opt_muxtree.cc
@@ -84,7 +84,7 @@ struct OptMuxtreeWorker
 		//	.const_activated
 		for (auto cell : module->cells())
 		{
-			if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux")
+			if (cell->type == "$mux" || cell->type == "$pmux")
 			{
 				RTLIL::SigSpec sig_a = cell->getPort("\\A");
 				RTLIL::SigSpec sig_b = cell->getPort("\\B");
diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc
index 5f3c4d29..e2b4243d 100644
--- a/passes/opt/opt_reduce.cc
+++ b/passes/opt/opt_reduce.cc
@@ -312,7 +312,7 @@ struct OptReduceWorker
 			std::vector<RTLIL::Cell*> cells;
 
 			for (auto &it : module->cells_)
-				if ((it.second->type == "$mux" || it.second->type == "$pmux" || it.second->type == "$safe_pmux") && design->selected(module, it.second))
+				if ((it.second->type == "$mux" || it.second->type == "$pmux") && design->selected(module, it.second))
 					cells.push_back(it.second);
 
 			for (auto cell : cells)
diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc
index eb970329..e9a5e7fd 100644
--- a/passes/opt/opt_share.cc
+++ b/passes/opt/opt_share.cc
@@ -224,7 +224,6 @@ struct OptShareWorker
 		if (mode_nomux) {
 			ct.cell_types.erase("$mux");
 			ct.cell_types.erase("$pmux");
-			ct.cell_types.erase("$safe_pmux");
 		}
 
 		log("Finding identical cells in module `%s'.\n", module->name.c_str());
diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc
index 94649013..94d5d27b 100644
--- a/passes/tests/test_cell.cc
+++ b/passes/tests/test_cell.cc
@@ -176,7 +176,6 @@ struct TestCellPass : public Pass {
 		// cell_types["$pmux"] = "A";
 		// cell_types["$slice"] = "A";
 		// cell_types["$concat"] = "A";
-		// cell_types["$safe_pmux"] = "A";
 		// cell_types["$lut"] = "A";
 		// cell_types["$assert"] = "A";