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authorClifford Wolf <clifford@clifford.at>2014-07-17 12:12:04 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-17 12:12:04 +0200
commit1b00861d0a3bba0b609eecde504d8a4f2f9d973d (patch)
tree0b533780cef7653d9d934be7008af6107e9453fb /passes
parent274c51487937e3ca37c3520e98e996cb5918e982 (diff)
Improved opt_reduce handling of mem wr_en mux bits
Diffstat (limited to 'passes')
-rw-r--r--passes/opt/opt_reduce.cc23
1 files changed, 18 insertions, 5 deletions
diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc
index d5bcb7f0..1e91d160 100644
--- a/passes/opt/opt_reduce.cc
+++ b/passes/opt/opt_reduce.cc
@@ -186,11 +186,21 @@ struct OptReduceWorker
for (int i = 0; i < int(sig_y.size()); i++)
{
std::vector<RTLIL::SigBit> in_tuple;
+ bool all_tuple_bits_same = true;
+
in_tuple.push_back(sig_a.at(i));
- for (int j = i; j < int(sig_b.size()); j += int(sig_a.size()))
+ for (int j = i; j < int(sig_b.size()); j += int(sig_a.size())) {
+ if (sig_b.at(j) != sig_a.at(i))
+ all_tuple_bits_same = false;
in_tuple.push_back(sig_b.at(j));
+ }
- if (consolidated_in_tuples_map.count(in_tuple))
+ if (all_tuple_bits_same)
+ {
+ old_sig_conn.first.append_bit(sig_y.at(i));
+ old_sig_conn.second.append_bit(sig_a.at(i));
+ }
+ else if (consolidated_in_tuples_map.count(in_tuple))
{
old_sig_conn.first.append_bit(sig_y.at(i));
old_sig_conn.second.append_bit(consolidated_in_tuples_map.at(in_tuple));
@@ -206,7 +216,8 @@ struct OptReduceWorker
if (new_sig_y.size() != sig_y.size())
{
log(" Consolidated identical input bits for %s cell %s:\n", cell->type.c_str(), cell->name.c_str());
- log(" Old inputs: A=%s, B=%s\n", log_signal(cell->connections["\\A"]), log_signal(cell->connections["\\B"]));
+ log(" Old ports: A=%s, B=%s, Y=%s\n", log_signal(cell->connections["\\A"]),
+ log_signal(cell->connections["\\B"]), log_signal(cell->connections["\\Y"]));
cell->connections["\\A"] = RTLIL::SigSpec();
for (auto &in_tuple : consolidated_in_tuples)
@@ -217,11 +228,13 @@ struct OptReduceWorker
for (auto &in_tuple : consolidated_in_tuples)
cell->connections["\\B"].append(in_tuple.at(i));
- log(" New inputs: A=%s, B=%s\n", log_signal(cell->connections["\\A"]), log_signal(cell->connections["\\B"]));
-
cell->parameters["\\WIDTH"] = RTLIL::Const(new_sig_y.size());
cell->connections["\\Y"] = new_sig_y;
+ log(" New ports: A=%s, B=%s, Y=%s\n", log_signal(cell->connections["\\A"]),
+ log_signal(cell->connections["\\B"]), log_signal(cell->connections["\\Y"]));
+ log(" New connections: %s = %s\n", log_signal(old_sig_conn.first), log_signal(old_sig_conn.second));
+
module->connections.push_back(old_sig_conn);
module->check();