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authorClifford Wolf <clifford@clifford.at>2014-07-21 12:35:06 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-21 12:35:06 +0200
commit1d88f1cf9f2088de7825f5292db5b40d4f73d036 (patch)
treeef1eeba2dcddbe957dabb8147b2b81cdc0d2ecd3 /passes
parent3cb61d03f8722fddfa14877accae1b3ca51e3926 (diff)
Removed deprecated module->new_wire()
Diffstat (limited to 'passes')
-rw-r--r--passes/cmds/connect.cc2
-rw-r--r--passes/cmds/delete.cc2
-rw-r--r--passes/cmds/splice.cc4
-rw-r--r--passes/memory/memory_share.cc4
-rw-r--r--passes/sat/freduce.cc4
-rw-r--r--passes/sat/miter.cc12
-rw-r--r--passes/sat/share.cc26
-rw-r--r--passes/techmap/simplemap.cc8
8 files changed, 31 insertions, 31 deletions
diff --git a/passes/cmds/connect.cc b/passes/cmds/connect.cc
index 7da2b951..f99cb9b5 100644
--- a/passes/cmds/connect.cc
+++ b/passes/cmds/connect.cc
@@ -27,7 +27,7 @@ static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap &
{
CellTypes ct(design);
- RTLIL::Wire *dummy_wire = module->new_wire(sig.width, NEW_ID);
+ RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.width);
for (auto &it : module->cells)
for (auto &port : it.second->connections)
diff --git a/passes/cmds/delete.cc b/passes/cmds/delete.cc
index 1c02752c..ce6ac4af 100644
--- a/passes/cmds/delete.cc
+++ b/passes/cmds/delete.cc
@@ -30,7 +30,7 @@ struct DeleteWireWorker
sig.optimize();
for (auto &c : sig.chunks)
if (c.wire != NULL && delete_wires_p->count(c.wire->name)) {
- c.wire = module->new_wire(c.width, NEW_ID);
+ c.wire = module->addWire(NEW_ID, c.width);
c.offset = 0;
}
}
diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc
index 6d920dbc..a48a54a1 100644
--- a/passes/cmds/splice.cc
+++ b/passes/cmds/splice.cc
@@ -77,7 +77,7 @@ struct SpliceWorker
cell->parameters["\\A_WIDTH"] = sig_a.width;
cell->parameters["\\Y_WIDTH"] = sig.width;
cell->connections["\\A"] = sig_a;
- cell->connections["\\Y"] = module->new_wire(sig.width, NEW_ID);
+ cell->connections["\\Y"] = module->addWire(NEW_ID, sig.width);
new_sig = cell->connections["\\Y"];
module->add(cell);
}
@@ -138,7 +138,7 @@ struct SpliceWorker
cell->parameters["\\B_WIDTH"] = sig2.width;
cell->connections["\\A"] = new_sig;
cell->connections["\\B"] = sig2;
- cell->connections["\\Y"] = module->new_wire(new_sig.width + sig2.width, NEW_ID);
+ cell->connections["\\Y"] = module->addWire(NEW_ID, new_sig.width + sig2.width);
new_sig = cell->connections["\\Y"];
module->add(cell);
}
diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc
index dc015f96..578007a0 100644
--- a/passes/memory/memory_share.cc
+++ b/passes/memory/memory_share.cc
@@ -419,7 +419,7 @@ struct MemoryShareWorker
if (0) {
found_overlapping_bits_i_j:
log(" Creating collosion-detect logic for port %d.\n", j);
- RTLIL::SigSpec is_same_addr = module->new_wire(1, NEW_ID);
+ RTLIL::SigSpec is_same_addr = module->addWire(NEW_ID);
module->addEq(NEW_ID, addr, wr_ports[j]->connections.at("\\ADDR"), is_same_addr);
merged_en = mask_en_grouped(is_same_addr, merged_en, sigmap(wr_ports[j]->connections.at("\\EN")));
}
@@ -603,7 +603,7 @@ struct MemoryShareWorker
std::map<std::pair<RTLIL::SigBit, RTLIL::SigBit>, int> groups_en;
RTLIL::SigSpec grouped_last_en, grouped_this_en, en;
- RTLIL::Wire *grouped_en = module->new_wire(0, NEW_ID);
+ RTLIL::Wire *grouped_en = module->addWire(NEW_ID, 0);
for (int j = 0; j < int(this_en.size()); j++) {
std::pair<RTLIL::SigBit, RTLIL::SigBit> key(last_en[j], this_en[j]);
diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc
index d4b7b5c1..ac041564 100644
--- a/passes/sat/freduce.cc
+++ b/passes/sat/freduce.cc
@@ -707,7 +707,7 @@ struct FreduceWorker
log(" Connect slave%s: %s\n", grp[i].inverted ? " using inverter" : "", log_signal(grp[i].bit));
RTLIL::Cell *drv = drivers.at(grp[i].bit).first;
- RTLIL::Wire *dummy_wire = module->new_wire(1, NEW_ID);
+ RTLIL::Wire *dummy_wire = module->addWire(NEW_ID);
for (auto &port : drv->connections)
if (ct.cell_output(drv->type, port.first))
sigmap(port.second).replace(grp[i].bit, dummy_wire, &port.second);
@@ -716,7 +716,7 @@ struct FreduceWorker
{
if (inv_sig.width == 0)
{
- inv_sig = module->new_wire(1, NEW_ID);
+ inv_sig = module->addWire(NEW_ID);
RTLIL::Cell *inv_cell = new RTLIL::Cell;
inv_cell->name = NEW_ID;
diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc
index 0ef9e9aa..6e57fceb 100644
--- a/passes/sat/miter.cc
+++ b/passes/sat/miter.cc
@@ -164,7 +164,7 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
if (flag_ignore_gold_x)
{
- RTLIL::SigSpec gold_x = miter_module->new_wire(w2_gold->width, NEW_ID);
+ RTLIL::SigSpec gold_x = miter_module->addWire(NEW_ID, w2_gold->width);
for (int i = 0; i < w2_gold->width; i++) {
RTLIL::Cell *eqx_cell = new RTLIL::Cell;
eqx_cell->name = NEW_ID;
@@ -180,8 +180,8 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
miter_module->add(eqx_cell);
}
- RTLIL::SigSpec gold_masked = miter_module->new_wire(w2_gold->width, NEW_ID);
- RTLIL::SigSpec gate_masked = miter_module->new_wire(w2_gate->width, NEW_ID);
+ RTLIL::SigSpec gold_masked = miter_module->addWire(NEW_ID, w2_gold->width);
+ RTLIL::SigSpec gate_masked = miter_module->addWire(NEW_ID, w2_gate->width);
RTLIL::Cell *or_gold_cell = new RTLIL::Cell;
or_gold_cell->name = NEW_ID;
@@ -219,7 +219,7 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
eq_cell->parameters["\\B_SIGNED"] = 0;
eq_cell->connections["\\A"] = gold_masked;
eq_cell->connections["\\B"] = gate_masked;
- eq_cell->connections["\\Y"] = miter_module->new_wire(1, NEW_ID);
+ eq_cell->connections["\\Y"] = miter_module->addWire(NEW_ID);
this_condition = eq_cell->connections["\\Y"];
miter_module->add(eq_cell);
}
@@ -235,7 +235,7 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
eq_cell->parameters["\\B_SIGNED"] = 0;
eq_cell->connections["\\A"] = w2_gold;
eq_cell->connections["\\B"] = w2_gate;
- eq_cell->connections["\\Y"] = miter_module->new_wire(1, NEW_ID);
+ eq_cell->connections["\\Y"] = miter_module->addWire(NEW_ID);
this_condition = eq_cell->connections["\\Y"];
miter_module->add(eq_cell);
}
@@ -261,7 +261,7 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
reduce_cell->parameters["\\Y_WIDTH"] = 1;
reduce_cell->parameters["\\A_SIGNED"] = 0;
reduce_cell->connections["\\A"] = all_conditions;
- reduce_cell->connections["\\Y"] = miter_module->new_wire(1, NEW_ID);
+ reduce_cell->connections["\\Y"] = miter_module->addWire(NEW_ID);
all_conditions = reduce_cell->connections["\\Y"];
miter_module->add(reduce_cell);
}
diff --git a/passes/sat/share.cc b/passes/sat/share.cc
index 852d8078..42e59c47 100644
--- a/passes/sat/share.cc
+++ b/passes/sat/share.cc
@@ -276,11 +276,11 @@ struct ShareWorker
int a_width = std::max(a1.width, a2.width);
int y_width = std::max(y1.width, y2.width);
- if (a1.width != a_width) a1 = module->addPos(NEW_ID, a1, module->new_wire(a_width, NEW_ID), a_signed)->connections.at("\\Y");
- if (a2.width != a_width) a2 = module->addPos(NEW_ID, a2, module->new_wire(a_width, NEW_ID), a_signed)->connections.at("\\Y");
+ if (a1.width != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y");
+ if (a2.width != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y");
RTLIL::SigSpec a = module->Mux(NEW_ID, a2, a1, act);
- RTLIL::Wire *y = module->new_wire(y_width, NEW_ID);
+ RTLIL::Wire *y = module->addWire(NEW_ID, y_width);
RTLIL::Cell *supercell = new RTLIL::Cell;
supercell->name = NEW_ID;
@@ -375,24 +375,24 @@ struct ShareWorker
{
a_width = std::max(y_width, a_width);
- if (a1.width < y1.width) a1 = module->addPos(NEW_ID, a1, module->new_wire(y1.width, NEW_ID), true)->connections.at("\\Y");
- if (a2.width < y2.width) a2 = module->addPos(NEW_ID, a2, module->new_wire(y2.width, NEW_ID), true)->connections.at("\\Y");
+ if (a1.width < y1.width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, y1.width), true)->connections.at("\\Y");
+ if (a2.width < y2.width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, y2.width), true)->connections.at("\\Y");
- if (a1.width != a_width) a1 = module->addPos(NEW_ID, a1, module->new_wire(a_width, NEW_ID), false)->connections.at("\\Y");
- if (a2.width != a_width) a2 = module->addPos(NEW_ID, a2, module->new_wire(a_width, NEW_ID), false)->connections.at("\\Y");
+ if (a1.width != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), false)->connections.at("\\Y");
+ if (a2.width != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), false)->connections.at("\\Y");
}
else
{
- if (a1.width != a_width) a1 = module->addPos(NEW_ID, a1, module->new_wire(a_width, NEW_ID), a_signed)->connections.at("\\Y");
- if (a2.width != a_width) a2 = module->addPos(NEW_ID, a2, module->new_wire(a_width, NEW_ID), a_signed)->connections.at("\\Y");
+ if (a1.width != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y");
+ if (a2.width != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y");
}
- if (b1.width != b_width) b1 = module->addPos(NEW_ID, b1, module->new_wire(b_width, NEW_ID), b_signed)->connections.at("\\Y");
- if (b2.width != b_width) b2 = module->addPos(NEW_ID, b2, module->new_wire(b_width, NEW_ID), b_signed)->connections.at("\\Y");
+ if (b1.width != b_width) b1 = module->addPos(NEW_ID, b1, module->addWire(NEW_ID, b_width), b_signed)->connections.at("\\Y");
+ if (b2.width != b_width) b2 = module->addPos(NEW_ID, b2, module->addWire(NEW_ID, b_width), b_signed)->connections.at("\\Y");
RTLIL::SigSpec a = module->Mux(NEW_ID, a2, a1, act);
RTLIL::SigSpec b = module->Mux(NEW_ID, b2, b1, act);
- RTLIL::Wire *y = module->new_wire(y_width, NEW_ID);
+ RTLIL::Wire *y = module->addWire(NEW_ID, y_width);
RTLIL::Cell *supercell = module->addCell(NEW_ID, c1->type);
supercell->parameters["\\A_SIGNED"] = a_signed;
@@ -617,7 +617,7 @@ struct ShareWorker
RTLIL::SigSpec make_cell_activation_logic(const std::set<std::pair<RTLIL::SigSpec, RTLIL::Const>> &activation_patterns)
{
- RTLIL::Wire *all_cases_wire = module->new_wire(0, NEW_ID);
+ RTLIL::Wire *all_cases_wire = module->addWire(NEW_ID, 0);
for (auto &p : activation_patterns) {
all_cases_wire->width++;
module->addEq(NEW_ID, p.first, p.second, RTLIL::SigSpec(all_cases_wire, 1, all_cases_wire->width - 1));
diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc
index e67b1e05..91f3b612 100644
--- a/passes/techmap/simplemap.cc
+++ b/passes/techmap/simplemap.cc
@@ -89,7 +89,7 @@ static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
if (cell->type == "$xnor")
{
- RTLIL::SigSpec sig_t = module->new_wire(width, NEW_ID);
+ RTLIL::SigSpec sig_t = module->addWire(NEW_ID, width);
sig_t.expand();
for (int i = 0; i < width; i++) {
@@ -158,7 +158,7 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
while (sig_a.width > 1)
{
- RTLIL::SigSpec sig_t = module->new_wire(sig_a.width / 2, NEW_ID);
+ RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig_a.width / 2);
sig_t.expand();
for (int i = 0; i < sig_a.width; i += 2)
@@ -182,7 +182,7 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
}
if (cell->type == "$reduce_xnor") {
- RTLIL::SigSpec sig_t = module->new_wire(1, NEW_ID);
+ RTLIL::SigSpec sig_t = module->addWire(NEW_ID);
RTLIL::Cell *gate = new RTLIL::Cell;
gate->name = NEW_ID;
gate->type = "$_INV_";
@@ -206,7 +206,7 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig)
while (sig.width > 1)
{
- RTLIL::SigSpec sig_t = module->new_wire(sig.width / 2, NEW_ID);
+ RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig.width / 2);
sig_t.expand();
for (int i = 0; i < sig.width; i += 2)