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authorJohann Glaser <Johann.Glaser@gmx.at>2014-05-28 18:05:38 +0200
committerJohann Glaser <Johann.Glaser@gmx.at>2014-05-28 18:05:38 +0200
commit278085fa01a9013051fbec842314cb6b5642e9bb (patch)
treec513abc708a19889f561d5df2875b6bd53e92fd9 /passes
parent63dfbb18cfb34d72746565a3eb3ffbcd7451cdab (diff)
added log_header to miter and expose pass, show cell type for exposed ports
Diffstat (limited to 'passes')
-rw-r--r--passes/sat/expose.cc8
-rw-r--r--passes/sat/miter.cc4
2 files changed, 9 insertions, 3 deletions
diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc
index 2ac7b35f..831a43aa 100644
--- a/passes/sat/expose.cc
+++ b/passes/sat/expose.cc
@@ -259,6 +259,8 @@ struct ExposePass : public Pass {
bool flag_evert_dff = false;
std::string sep = ".";
+ log_header("Executing EXPOSE pass (exposing internal signals as outputs).\n");
+
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{
@@ -629,7 +631,7 @@ struct ExposePass : public Pass {
w->port_input = true;
add_new_wire(module, w);
- log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name));
+ log("New module port: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name), RTLIL::id2cstr(cell->type));
RTLIL::SigSpec sig;
if (cell->connections.count(p->name) != 0)
@@ -654,7 +656,7 @@ struct ExposePass : public Pass {
w->port_input = true;
add_new_wire(module, w);
- log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name));
+ log("New module port: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name), RTLIL::id2cstr(cell->type));
if (w->port_input)
module->connections.push_back(RTLIL::SigSig(it.second, w));
@@ -667,7 +669,7 @@ struct ExposePass : public Pass {
}
for (auto &it : delete_cells) {
- log("Removing cell: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(it));
+ log("Removing cell: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(it), RTLIL::id2cstr(module->cells.at(it)->type));
delete module->cells.at(it);
module->cells.erase(it);
}
diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc
index db12cb57..6c8e2ff4 100644
--- a/passes/sat/miter.cc
+++ b/passes/sat/miter.cc
@@ -28,6 +28,8 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
bool flag_make_outcmp = false;
bool flag_make_assert = false;
+ log_header("Executing MITER pass (creating miter circuit).\n");
+
size_t argidx;
for (argidx = 2; argidx < args.size(); argidx++)
{
@@ -102,6 +104,8 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
log_cmd_error("No matching port in gold module was found for %s!\n", it.second->name.c_str());
}
+ log("Creating miter cell \"%s\" with gold cell \"%s\" and gate cell \"%s\".\n", RTLIL::id2cstr(miter_name), RTLIL::id2cstr(gold_name), RTLIL::id2cstr(gate_name));
+
RTLIL::Module *miter_module = new RTLIL::Module;
miter_module->name = miter_name;
design->modules[miter_name] = miter_module;