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authorClifford Wolf <clifford@clifford.at>2013-11-24 05:03:43 +0100
committerClifford Wolf <clifford@clifford.at>2013-11-24 05:03:43 +0100
commit28093d9dd288484daa9df17585c1c9f174498359 (patch)
tree3940c6d3bd95f7c983c76cd6e54bd04216867f3d /passes
parenta4edecb0cae0524b6f42d1a2c64af5a940c67a2f (diff)
Added "top" attribute to mark top module in hierarchy
Diffstat (limited to 'passes')
-rw-r--r--passes/hierarchy/hierarchy.cc17
-rw-r--r--passes/techmap/techmap.cc29
2 files changed, 43 insertions, 3 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index b98afcc1..d9b52c6d 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -280,6 +280,10 @@ struct HierarchyPass : public Pass {
log(" use the specified top module to built a design hierarchy. modules\n");
log(" outside this tree (unused modules) are removed.\n");
log("\n");
+ log(" when the -top option is used, the 'top' attribute will be set on the\n");
+ log(" specified top module. otherwise a module with the 'top' attribute set\n");
+ log(" will implicitly be used as top module, if such a module exists.\n");
+ log("\n");
log("In -generate mode this pass generates blackbox modules for the given cell\n");
log("types (wildcards supported). For this the design is searched for cells that\n");
log("match the given types and then the given port declarations are used to\n");
@@ -381,6 +385,11 @@ struct HierarchyPass : public Pass {
log_push();
+ if (top_mod == NULL)
+ for (auto &mod_it : design->modules)
+ if (mod_it.second->get_bool_attribute("\\top"))
+ top_mod = mod_it.second;
+
if (top_mod != NULL)
hierarchy(design, top_mod);
@@ -407,6 +416,14 @@ struct HierarchyPass : public Pass {
hierarchy(design, top_mod);
}
+ if (top_mod != NULL) {
+ for (auto &mod_it : design->modules)
+ if (mod_it.second == top_mod)
+ mod_it.second->attributes["\\top"] = RTLIL::Const(1);
+ else
+ mod_it.second->attributes.erase("\\top");
+ }
+
if (!keep_positionals)
{
std::set<RTLIL::Module*> pos_mods;
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index e273769d..7e3ba23e 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -500,19 +500,42 @@ struct FlattenPass : public Pass {
for (auto &it : design->modules)
celltypeMap[it.first].insert(it.first);
+ RTLIL::Module *top_mod = NULL;
+ for (auto &mod_it : design->modules)
+ if (mod_it.second->get_bool_attribute("\\top"))
+ top_mod = mod_it.second;
+
bool did_something = true;
std::set<RTLIL::Cell*> handled_cells;
while (did_something) {
did_something = false;
- for (auto &mod_it : design->modules)
- if (techmap_module(design, mod_it.second, design, handled_cells, celltypeMap, true))
+ if (top_mod != NULL) {
+ if (techmap_module(design, top_mod, design, handled_cells, celltypeMap, true))
did_something = true;
+ } else {
+ for (auto &mod_it : design->modules)
+ if (techmap_module(design, mod_it.second, design, handled_cells, celltypeMap, true))
+ did_something = true;
+ }
}
log("No more expansions possible.\n");
+
+ if (top_mod != NULL) {
+ std::map<RTLIL::IdString, RTLIL::Module*> new_modules;
+ for (auto &mod_it : design->modules)
+ if (mod_it.second == top_mod) {
+ new_modules[mod_it.first] = mod_it.second;
+ } else {
+ log("Deleting now unused module %s.\n", RTLIL::id2cstr(mod_it.first));
+ delete mod_it.second;
+ }
+ design->modules.swap(new_modules);
+ }
+
techmap_cache.clear();
techmap_do_cache.clear();
log_pop();
}
} FlattenPass;
-
+