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authorClifford Wolf <clifford@clifford.at>2013-11-22 15:01:12 +0100
committerClifford Wolf <clifford@clifford.at>2013-11-22 15:01:12 +0100
commit295e352ba6aa1bd71431abc21a8f93735968cae6 (patch)
tree2261f6a66d6fa1e7f67d2aa220f6e4f588be4cea /passes
parentc854ad2e7ecae6115182e9210f2b6c57afa98c23 (diff)
Renamed "placeholder" to "blackbox"
Diffstat (limited to 'passes')
-rw-r--r--passes/cmds/add.cc4
-rw-r--r--passes/cmds/show.cc6
-rw-r--r--passes/hierarchy/hierarchy.cc6
-rw-r--r--passes/techmap/dfflibmap.cc2
4 files changed, 9 insertions, 9 deletions
diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc
index 12706c4f..acee4c46 100644
--- a/passes/cmds/add.cc
+++ b/passes/cmds/add.cc
@@ -73,7 +73,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
RTLIL::Module *mod = design->modules.at(it.second->type);
if (!design->selected_whole_module(mod->name))
continue;
- if (mod->get_bool_attribute("\\placeholder"))
+ if (mod->get_bool_attribute("\\blackbox"))
continue;
if (it.second->connections.count(name) > 0)
continue;
@@ -144,7 +144,7 @@ struct AddPass : public Pass {
RTLIL::Module *module = mod.second;
if (!design->selected_whole_module(module->name))
continue;
- if (module->get_bool_attribute("\\placeholder"))
+ if (module->get_bool_attribute("\\blackbox"))
continue;
if (command == "wire")
diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc
index 583b8da9..adb925cb 100644
--- a/passes/cmds/show.cc
+++ b/passes/cmds/show.cc
@@ -477,8 +477,8 @@ struct ShowWorker
if (!design->selected_module(module->name))
continue;
if (design->selected_whole_module(module->name)) {
- if (module->get_bool_attribute("\\placeholder")) {
- log("Skipping placeholder module %s.\n", id2cstr(module->name));
+ if (module->get_bool_attribute("\\blackbox")) {
+ log("Skipping blackbox module %s.\n", id2cstr(module->name));
continue;
} else
if (module->cells.empty() && module->connections.empty() && module->processes.empty()) {
@@ -617,7 +617,7 @@ struct ShowPass : public Pass {
if (format != "ps") {
int modcount = 0;
for (auto &mod_it : design->modules) {
- if (mod_it.second->get_bool_attribute("\\placeholder"))
+ if (mod_it.second->get_bool_attribute("\\blackbox"))
continue;
if (mod_it.second->cells.empty() && mod_it.second->connections.empty())
continue;
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index 7291aa80..b98afcc1 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -113,7 +113,7 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
RTLIL::Module *mod = new RTLIL::Module;
mod->name = celltype;
- mod->attributes["\\placeholder"] = RTLIL::Const(1);
+ mod->attributes["\\blackbox"] = RTLIL::Const(1);
design->modules[mod->name] = mod;
for (auto &decl : ports) {
@@ -147,7 +147,7 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla
}
if (cell->parameters.size() == 0)
continue;
- if (design->modules.at(cell->type)->get_bool_attribute("\\placeholder"))
+ if (design->modules.at(cell->type)->get_bool_attribute("\\blackbox"))
continue;
RTLIL::Module *mod = design->modules[cell->type];
cell->type = mod->derive(design, cell->parameters);
@@ -280,7 +280,7 @@ struct HierarchyPass : public Pass {
log(" use the specified top module to built a design hierarchy. modules\n");
log(" outside this tree (unused modules) are removed.\n");
log("\n");
- log("In -generate mode this pass generates placeholder modules for the given cell\n");
+ log("In -generate mode this pass generates blackbox modules for the given cell\n");
log("types (wildcards supported). For this the design is searched for cells that\n");
log("match the given types and then the given port declarations are used to\n");
log("determine the direction of the ports. The syntax for a port declaration is:\n");
diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc
index bebf7ce6..0324afa8 100644
--- a/passes/techmap/dfflibmap.cc
+++ b/passes/techmap/dfflibmap.cc
@@ -498,7 +498,7 @@ struct DfflibmapPass : public Pass {
logmap_all();
for (auto &it : design->modules)
- if (design->selected(it.second) && !it.second->get_bool_attribute("\\placeholder"))
+ if (design->selected(it.second) && !it.second->get_bool_attribute("\\blackbox"))
dfflibmap(design, it.second);
cell_mappings.clear();