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authorClifford Wolf <clifford@clifford.at>2013-12-27 14:20:15 +0100
committerClifford Wolf <clifford@clifford.at>2013-12-27 14:20:15 +0100
commit369bf81a7049c96f62af084bb5007fbf45e36ab4 (patch)
tree92071580c9bd60888ee5861d59457947a8adfde7 /passes
parentecc30255ba70910777a4586f5bd6abc818073293 (diff)
Added support for non-const === and !== (for miter circuits)
Diffstat (limited to 'passes')
-rw-r--r--passes/extract/extract.cc2
-rw-r--r--passes/opt/opt_const.cc12
-rw-r--r--passes/proc/proc_arst.cc4
3 files changed, 11 insertions, 7 deletions
diff --git a/passes/extract/extract.cc b/passes/extract/extract.cc
index 0c639aed..aa21e573 100644
--- a/passes/extract/extract.cc
+++ b/passes/extract/extract.cc
@@ -499,6 +499,8 @@ struct ExtractPass : public Pass {
solver.addSwappablePorts("$xnor", "\\A", "\\B");
solver.addSwappablePorts("$eq", "\\A", "\\B");
solver.addSwappablePorts("$ne", "\\A", "\\B");
+ solver.addSwappablePorts("$eqx", "\\A", "\\B");
+ solver.addSwappablePorts("$nex", "\\A", "\\B");
solver.addSwappablePorts("$add", "\\A", "\\B");
solver.addSwappablePorts("$mul", "\\A", "\\B");
solver.addSwappablePorts("$logic_and", "\\A", "\\B");
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc
index b7b361e9..30d85588 100644
--- a/passes/opt/opt_const.cc
+++ b/passes/opt/opt_const.cc
@@ -144,7 +144,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
#endif
}
- if (cell->type == "$eq" || cell->type == "$ne")
+ if (cell->type == "$eq" || cell->type == "$ne" || cell->type == "$eqx" || cell->type == "$nex")
{
RTLIL::SigSpec a = cell->connections["\\A"];
RTLIL::SigSpec b = cell->connections["\\B"];
@@ -160,10 +160,12 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
assert(a.chunks.size() == b.chunks.size());
for (size_t i = 0; i < a.chunks.size(); i++) {
- if (a.chunks[i].wire == NULL && a.chunks[i].data.bits[0] > RTLIL::State::S1)
- continue;
- if (b.chunks[i].wire == NULL && b.chunks[i].data.bits[0] > RTLIL::State::S1)
- continue;
+ if (cell->type == "$eq" || cell->type == "$ne") {
+ if (a.chunks[i].wire == NULL && a.chunks[i].data.bits[0] > RTLIL::State::S1)
+ continue;
+ if (b.chunks[i].wire == NULL && b.chunks[i].data.bits[0] > RTLIL::State::S1)
+ continue;
+ }
new_a.append(a.chunks[i]);
new_b.append(b.chunks[i]);
}
diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc
index 65dc97bd..57194657 100644
--- a/passes/proc/proc_arst.cc
+++ b/passes/proc/proc_arst.cc
@@ -47,7 +47,7 @@ static bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSp
polarity = !polarity;
return check_signal(mod, cell->connections["\\A"], ref, polarity);
}
- if (cell->type == "$eq" && cell->connections["\\Y"] == signal) {
+ if ((cell->type == "$eq" || cell->type == "$eqx") && cell->connections["\\Y"] == signal) {
if (cell->connections["\\A"].is_fully_const()) {
if (!cell->connections["\\A"].as_bool())
polarity = !polarity;
@@ -59,7 +59,7 @@ static bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSp
return check_signal(mod, cell->connections["\\A"], ref, polarity);
}
}
- if (cell->type == "$ne" && cell->connections["\\Y"] == signal) {
+ if ((cell->type == "$ne" || cell->type == "$nex") && cell->connections["\\Y"] == signal) {
if (cell->connections["\\A"].is_fully_const()) {
if (cell->connections["\\A"].as_bool())
polarity = !polarity;