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authorClifford Wolf <clifford@clifford.at>2015-01-02 00:07:44 +0100
committerClifford Wolf <clifford@clifford.at>2015-01-02 00:07:44 +0100
commit36c20f2ede51580f7c68b96b9cde9473187a8fc6 (patch)
treeecf8843a6c1abdbf2757cb55539d4377357d83c0 /passes
parent24ae156a747d5b933693878e7f2ed4c311e36570 (diff)
Progress in memory_bram
Diffstat (limited to 'passes')
-rw-r--r--passes/memory/memory_bram.cc11
1 files changed, 10 insertions, 1 deletions
diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc
index d33db120..853950a3 100644
--- a/passes/memory/memory_bram.cc
+++ b/passes/memory/memory_bram.cc
@@ -30,6 +30,7 @@ struct rules_t
SigBit sig_clock;
SigSpec sig_addr, sig_data, sig_en;
+ bool effective_clkpol;
int mapped_port;
};
@@ -320,6 +321,7 @@ bool replace_cell(Cell *cell, const rules_t::bram_t &bram, const rules_t::match_
if (clken) {
clock_domains[pi.clocks] = clkdom;
pi.sig_clock = clkdom.first;
+ pi.effective_clkpol = clkdom.second;
}
pi.sig_en = sig_en;
@@ -405,6 +407,7 @@ grow_read_ports:;
if (clken) {
clock_domains[pi.clocks] = clkdom;
pi.sig_clock = clkdom.first;
+ pi.effective_clkpol = clkdom.second;
}
pi.sig_addr = rd_addr.extract(cell_port_i*mem_abits, mem_abits);
@@ -483,7 +486,13 @@ grow_read_ports:;
bram_dout.remove(i);
}
- dout_cache[sig_data].first.append(addr_ok);
+ SigSpec addr_ok_q = addr_ok;
+ if (pi.clocks && !addr_ok.empty()) {
+ addr_ok_q = module->addWire(NEW_ID);
+ module->addDff(NEW_ID, pi.sig_clock, addr_ok, addr_ok_q, pi.effective_clkpol);
+ }
+
+ dout_cache[sig_data].first.append(addr_ok_q);
dout_cache[sig_data].second.append(bram_dout);
}