summaryrefslogtreecommitdiff
path: root/passes
diff options
context:
space:
mode:
authorClifford Wolf <clifford@clifford.at>2014-09-19 13:15:31 +0200
committerClifford Wolf <clifford@clifford.at>2014-09-19 13:15:31 +0200
commit3aa003c8e9c207758797e533cb85514cdb0db2c6 (patch)
treef45e1fd3e5a002ace3ac9415e70cf32edeb4b247 /passes
parentf7bb8f244beff135aa2ef6c771bece45ce240c5d (diff)
Using "NOT" instead of "INV" as cell name in default abc genlib file
Diffstat (limited to 'passes')
-rw-r--r--passes/abc/abc.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc
index d99eff7d..75368e3c 100644
--- a/passes/abc/abc.cc
+++ b/passes/abc/abc.cc
@@ -712,7 +712,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
fprintf(f, "GATE ZERO 1 Y=CONST0;\n");
fprintf(f, "GATE ONE 1 Y=CONST1;\n");
fprintf(f, "GATE BUF 1 Y=A; PIN * NONINV 1 999 1 0 1 0\n");
- fprintf(f, "GATE INV 1 Y=!A; PIN * INV 1 999 1 0 1 0\n");
+ fprintf(f, "GATE NOT 1 Y=!A; PIN * INV 1 999 1 0 1 0\n");
fprintf(f, "GATE AND 1 Y=A*B; PIN * NONINV 1 999 1 0 1 0\n");
fprintf(f, "GATE NAND 1 Y=!(A*B); PIN * INV 1 999 1 0 1 0\n");
fprintf(f, "GATE OR 1 Y=A+B; PIN * NONINV 1 999 1 0 1 0\n");
@@ -854,7 +854,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
module->connect(conn);
continue;
}
- if (c->type == "\\INV") {
+ if (c->type == "\\NOT") {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_NOT_");
cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));