summaryrefslogtreecommitdiff
path: root/passes
diff options
context:
space:
mode:
authorClifford Wolf <clifford@clifford.at>2014-08-16 19:44:31 +0200
committerClifford Wolf <clifford@clifford.at>2014-08-16 19:44:31 +0200
commit3b9157f9a605b5ae2f535c4da932891e504dc57e (patch)
tree27383290ca3902e65b989d3f2d358ac5d8cc1cd8 /passes
parent83e2698e10065a27afcc0f0db3818ed3b4a5942e (diff)
Added "test_cell -s <seed>"
Diffstat (limited to 'passes')
-rw-r--r--passes/tests/test_cell.cc22
1 files changed, 17 insertions, 5 deletions
diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc
index 94d5d27b..a4b8be0c 100644
--- a/passes/tests/test_cell.cc
+++ b/passes/tests/test_cell.cc
@@ -21,12 +21,13 @@
#include "kernel/yosys.h"
#include <algorithm>
+static uint32_t xorshift32_state = 123456789;
+
static uint32_t xorshift32(uint32_t limit) {
- static uint32_t x = 123456789;
- x ^= x << 13;
- x ^= x >> 17;
- x ^= x << 5;
- return x % limit;
+ xorshift32_state ^= xorshift32_state << 13;
+ xorshift32_state ^= xorshift32_state >> 17;
+ xorshift32_state ^= xorshift32_state << 5;
+ return xorshift32_state % limit;
}
static void create_gold_module(RTLIL::Design *design, std::string cell_type, std::string cell_type_flags)
@@ -94,6 +95,9 @@ struct TestCellPass : public Pass {
log(" -n {integer}\n");
log(" create this number of cell instances and test them (default = 100).\n");
log("\n");
+ log(" -s {positive_integer}\n");
+ log(" use this value as rng seed value (default = unix time).\n");
+ log("\n");
log(" -f {ilang_file}\n");
log(" don't generate circuits. instead load the specified ilang file.\n");
log("\n");
@@ -106,6 +110,7 @@ struct TestCellPass : public Pass {
int num_iter = 100;
std::string techmap_cmd = "techmap -assert";
std::string ilang_file;
+ xorshift32_state = 0;
int argidx;
for (argidx = 1; argidx < SIZE(args); argidx++)
@@ -114,6 +119,10 @@ struct TestCellPass : public Pass {
num_iter = atoi(args[++argidx].c_str());
continue;
}
+ if (args[argidx] == "-s" && argidx+1 < SIZE(args)) {
+ xorshift32_state = atoi(args[++argidx].c_str());
+ continue;
+ }
if (args[argidx] == "-map" && argidx+1 < SIZE(args)) {
techmap_cmd += " -map " + args[++argidx];
continue;
@@ -126,6 +135,9 @@ struct TestCellPass : public Pass {
break;
}
+ if (xorshift32_state == 0)
+ xorshift32_state = time(NULL);
+
std::map<std::string, std::string> cell_types;
std::vector<std::string> selected_cell_types;