Added dict/pool.sort()

2 files changed, 6 insertions, 0 deletions

diff --git a/passes/equiv/equiv_induct.cc b/passes/equiv/equiv_induct.cc
index 38a52d75..01b92204 100644
--- a/passes/equiv/equiv_induct.cc
+++ b/passes/equiv/equiv_induct.cc
@@ -100,6 +100,8 @@ struct EquivInductWorker
 			log("  Proof for induction step failed. %s\n", step != max_seq ? "Extending to next time step." : "Trying to prove individual $equiv from workset.");
 		}
 
+		workset.sort();
+
 		for (auto cell : workset)
 		{
 			SigBit bit_a = sigmap(cell->getPort("\\A")).to_single_sigbit();
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index c5b25816..98f83dff 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -422,6 +422,10 @@ struct CleanPass : public Pass {
 		if (count_rm_cells > 0 || count_rm_wires > 0)
 			log("Removed %d unused cells and %d unused wires.\n", count_rm_cells, count_rm_wires);
 
+		design->optimize();
+		design->sort();
+		design->check();
+
 		ct.clear();
 		ct_reg.clear();
 		ct_all.clear();