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authorClifford Wolf <clifford@clifford.at>2015-01-06 00:16:44 +0100
committerClifford Wolf <clifford@clifford.at>2015-01-06 00:16:44 +0100
commit462b22f44fae71767991bd4eb502d009149b3995 (patch)
tree2cd6e77f9d0e377d566c072a6ea0b13dc9a932fc /passes
parent9ea2511fe87a9a3a4dd179101f42982ed62e78c0 (diff)
dict<> ref vs insert bugfix
Diffstat (limited to 'passes')
-rw-r--r--passes/opt/opt_const.cc23
1 files changed, 13 insertions, 10 deletions
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc
index 7f800bde..2eaba15c 100644
--- a/passes/opt/opt_const.cc
+++ b/passes/opt/opt_const.cc
@@ -669,8 +669,9 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
cell->unsetPort("\\B");
cell->unsetPort("\\S");
if (cell->type == "$mux") {
- cell->parameters["\\A_WIDTH"] = cell->parameters["\\WIDTH"];
- cell->parameters["\\Y_WIDTH"] = cell->parameters["\\WIDTH"];
+ Const width = cell->parameters["\\WIDTH"];
+ cell->parameters["\\A_WIDTH"] = width;
+ cell->parameters["\\Y_WIDTH"] = width;
cell->parameters["\\A_SIGNED"] = 0;
cell->parameters.erase("\\WIDTH");
cell->type = "$not";
@@ -686,9 +687,10 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
cell->setPort("\\A", cell->getPort("\\S"));
cell->unsetPort("\\S");
if (cell->type == "$mux") {
- cell->parameters["\\A_WIDTH"] = cell->parameters["\\WIDTH"];
- cell->parameters["\\B_WIDTH"] = cell->parameters["\\WIDTH"];
- cell->parameters["\\Y_WIDTH"] = cell->parameters["\\WIDTH"];
+ auto width = cell->parameters["\\WIDTH"];
+ cell->parameters["\\A_WIDTH"] = width;
+ cell->parameters["\\B_WIDTH"] = width;
+ cell->parameters["\\Y_WIDTH"] = width;
cell->parameters["\\A_SIGNED"] = 0;
cell->parameters["\\B_SIGNED"] = 0;
cell->parameters.erase("\\WIDTH");
@@ -705,9 +707,10 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
cell->setPort("\\B", cell->getPort("\\S"));
cell->unsetPort("\\S");
if (cell->type == "$mux") {
- cell->parameters["\\A_WIDTH"] = cell->parameters["\\WIDTH"];
- cell->parameters["\\B_WIDTH"] = cell->parameters["\\WIDTH"];
- cell->parameters["\\Y_WIDTH"] = cell->parameters["\\WIDTH"];
+ auto width = cell->parameters["\\WIDTH"];
+ cell->parameters["\\A_WIDTH"] = width;
+ cell->parameters["\\B_WIDTH"] = width;
+ cell->parameters["\\Y_WIDTH"] = width;
cell->parameters["\\A_SIGNED"] = 0;
cell->parameters["\\B_SIGNED"] = 0;
cell->parameters.erase("\\WIDTH");
@@ -894,8 +897,8 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (!swapped_ab) {
cell->setPort("\\A", cell->getPort("\\B"));
- cell->parameters["\\A_WIDTH"] = cell->parameters["\\B_WIDTH"];
- cell->parameters["\\A_SIGNED"] = cell->parameters["\\B_SIGNED"];
+ cell->parameters.at("\\A_WIDTH") = cell->parameters.at("\\B_WIDTH");
+ cell->parameters.at("\\A_SIGNED") = cell->parameters.at("\\B_SIGNED");
}
std::vector<RTLIL::SigBit> new_b = RTLIL::SigSpec(i, 6);