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authorClifford Wolf <clifford@clifford.at>2013-06-20 12:49:28 +0200
committerClifford Wolf <clifford@clifford.at>2013-06-20 12:49:28 +0200
commit46b177eb8a7a9e52eee4fd2e4a86c56f9a1fb44a (patch)
tree13fd0b6690e8419e68c2a794ceb26fcc9c8f5ca6 /passes
parent8fbb5b62400edf82f6719eda90a75730d467db83 (diff)
parenta6aeb3dbf03eb9f09f57ded48d13e72241589374 (diff)
Merge branch 'master' of github.com:cliffordwolf/yosys
Diffstat (limited to 'passes')
-rw-r--r--passes/cmds/rename.cc30
1 files changed, 28 insertions, 2 deletions
diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc
index c2ef5e69..906256a1 100644
--- a/passes/cmds/rename.cc
+++ b/passes/cmds/rename.cc
@@ -21,9 +21,35 @@
#include "kernel/rtlil.h"
#include "kernel/log.h"
-static void rename_in_module(RTLIL::Module*, std::string, std::string)
+static void rename_in_module(RTLIL::Module *module, std::string from_name, std::string to_name)
{
- log_cmd_error("Sorry: Only renaming of modules is implemented at the moment.\n");
+ from_name = RTLIL::escape_id(from_name);
+ to_name = RTLIL::escape_id(to_name);
+
+ if (module->count_id(to_name))
+ log_cmd_error("There is already an object `%s' in module `%s'.\n", to_name.c_str(), module->name.c_str());
+
+ for (auto &it : module->wires)
+ if (it.first == from_name) {
+ RTLIL::Wire *wire = it.second;
+ log("Renaming wire %s to %s in module %s.\n", wire->name.c_str(), to_name.c_str(), module->name.c_str());
+ module->wires.erase(wire->name);
+ wire->name = to_name;
+ module->add(wire);
+ return;
+ }
+
+ for (auto &it : module->cells)
+ if (it.first == from_name) {
+ RTLIL::Cell *cell = it.second;
+ log("Renaming cell %s to %s in module %s.\n", cell->name.c_str(), to_name.c_str(), module->name.c_str());
+ module->cells.erase(cell->name);
+ cell->name = to_name;
+ module->add(cell);
+ return;
+ }
+
+ log_cmd_error("Object `%s' not found!\n", from_name.c_str());
}
struct RenamePass : public Pass {