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authorClifford Wolf <clifford@clifford.at>2015-01-06 14:37:50 +0100
committerClifford Wolf <clifford@clifford.at>2015-01-06 14:37:50 +0100
commit4a0b3a5423175eed7f1de9e975ee1fb20a2eb3ae (patch)
treedbd46dac402b656233bad522637c1410284aa450 /passes
parent081e1a49f81c298a5c30c4b51241d50ce64f185e (diff)
Various small improvements to synth_xilinx
Diffstat (limited to 'passes')
-rw-r--r--passes/techmap/iopadmap.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc
index 76d6115a..75d02c82 100644
--- a/passes/techmap/iopadmap.cc
+++ b/passes/techmap/iopadmap.cc
@@ -62,8 +62,8 @@ struct IopadmapPass : public Pass {
log("\n");
log(" -bits\n");
log(" create individual bit-wide buffers even for ports that\n");
- log(" are wider. (the default behavio is to create word-wide\n");
- log(" buffers use -widthparam to set the word size on the cell.)\n");
+ log(" are wider. (the default behavior is to create word-wide\n");
+ log(" buffers using -widthparam to set the word size on the cell.)\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)