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authorClifford Wolf <clifford@clifford.at>2013-11-23 16:49:58 +0100
committerClifford Wolf <clifford@clifford.at>2013-11-23 16:49:58 +0100
commit5f9c7fc6eadd7bc70e13df4131c059ec9ae18103 (patch)
treef535b084aee342eb21dcfc1f9a6bed16ce87db6b /passes
parent1de12e1efc9d346d4c1847ddf9a85c38e9b503ee (diff)
Improved handling of techmap special wires
Diffstat (limited to 'passes')
-rw-r--r--passes/techmap/techmap.cc4
1 files changed, 3 insertions, 1 deletions
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 0bc19c34..e273769d 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -78,7 +78,7 @@ static TechmapWires techmap_find_special_wires(RTLIL::Module *module)
record.value = it.second;
result[p].push_back(record);
it.second->attributes["\\keep"] = RTLIL::Const(1);
- it.second->attributes["\\_techmap_attr_"] = RTLIL::Const(1);
+ it.second->attributes["\\_techmap_special_"] = RTLIL::Const(1);
}
}
@@ -112,6 +112,8 @@ static void techmap_module_worker(RTLIL::Design *design, RTLIL::Module *module,
w->port_input = false;
w->port_output = false;
w->port_id = 0;
+ if (it.second->get_bool_attribute("\\_techmap_special_"))
+ w->attributes.clear();
module->wires[w->name] = w;
design->select(module, w);
}