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authorClifford Wolf <clifford@clifford.at>2013-06-14 10:31:18 +0200
committerClifford Wolf <clifford@clifford.at>2013-06-14 17:50:26 +0200
commit6d7b5f90641169d60113b618ad127c7568d13dce (patch)
tree4d62a61bde6a2cce70a712362d5893b9b3edae37 /passes
parent30db70b1baaad1f299234b419ac2dc581eee1e14 (diff)
Fixed even more ConstEval bugs found using xsthammer
Diffstat (limited to 'passes')
-rw-r--r--passes/sat/sat.cc3
1 files changed, 1 insertions, 2 deletions
diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc
index b192ac01..69b6006d 100644
--- a/passes/sat/sat.cc
+++ b/passes/sat/sat.cc
@@ -510,8 +510,7 @@ struct BruteForceEquivChecker
log_cmd_error("Port %s in module 1 has no counterpart in module 2!\n", wire1->name.c_str());
RTLIL::Wire *wire2 = mod2->wires.at(wire1->name);
- if (wire1->width != wire2->width || wire1->port_id != wire2->port_id ||
- wire1->port_input != wire2->port_input || wire1->port_output != wire2->port_output)
+ if (wire1->width != wire2->width || wire1->port_input != wire2->port_input || wire1->port_output != wire2->port_output)
log_cmd_error("Port %s in module 1 does not match its counterpart in module 2!\n", wire1->name.c_str());
if (wire1->port_input) {