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authorClifford Wolf <clifford@clifford.at>2015-10-24 22:56:40 +0200
committerClifford Wolf <clifford@clifford.at>2015-10-24 22:56:40 +0200
commit7f110e7018d35f29cf6a5d3031400a8044c8d32d (patch)
tree9c65e6929e43faec716efab17b37bd53f9afa4b3 /passes
parent6af80769678f260aa4aeaf3b12b54dfdc15fa5dd (diff)
renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit()
Diffstat (limited to 'passes')
-rw-r--r--passes/cmds/splice.cc2
-rw-r--r--passes/equiv/equiv_induct.cc8
-rw-r--r--passes/equiv/equiv_simple.cc6
-rw-r--r--passes/fsm/fsm_opt.cc2
-rw-r--r--passes/sat/expose.cc20
5 files changed, 19 insertions, 19 deletions
diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc
index 4ce2ec11..2556fb74 100644
--- a/passes/cmds/splice.cc
+++ b/passes/cmds/splice.cc
@@ -64,7 +64,7 @@ struct SpliceWorker
return sliced_signals_cache.at(sig);
int offset = 0;
- int p = driven_bits_map.at(sig.extract(0, 1).to_single_sigbit()) - 1;
+ int p = driven_bits_map.at(sig.extract(0, 1).as_bit()) - 1;
while (driven_bits.at(p) != RTLIL::State::Sm)
p--, offset++;
diff --git a/passes/equiv/equiv_induct.cc b/passes/equiv/equiv_induct.cc
index a536fe30..cdb951ec 100644
--- a/passes/equiv/equiv_induct.cc
+++ b/passes/equiv/equiv_induct.cc
@@ -59,8 +59,8 @@ struct EquivInductWorker
cell_warn_cache.insert(cell);
}
if (cell->type == "$equiv") {
- SigBit bit_a = sigmap(cell->getPort("\\A")).to_single_sigbit();
- SigBit bit_b = sigmap(cell->getPort("\\B")).to_single_sigbit();
+ SigBit bit_a = sigmap(cell->getPort("\\A")).as_bit();
+ SigBit bit_b = sigmap(cell->getPort("\\B")).as_bit();
if (bit_a != bit_b) {
int ez_a = satgen.importSigBit(bit_a, step);
int ez_b = satgen.importSigBit(bit_b, step);
@@ -137,8 +137,8 @@ struct EquivInductWorker
for (auto cell : workset)
{
- SigBit bit_a = sigmap(cell->getPort("\\A")).to_single_sigbit();
- SigBit bit_b = sigmap(cell->getPort("\\B")).to_single_sigbit();
+ SigBit bit_a = sigmap(cell->getPort("\\A")).as_bit();
+ SigBit bit_b = sigmap(cell->getPort("\\B")).as_bit();
log(" Trying to prove $equiv for %s:", log_signal(sigmap(cell->getPort("\\Y"))));
diff --git a/passes/equiv/equiv_simple.cc b/passes/equiv/equiv_simple.cc
index 1f52a632..fa22dc62 100644
--- a/passes/equiv/equiv_simple.cc
+++ b/passes/equiv/equiv_simple.cc
@@ -89,8 +89,8 @@ struct EquivSimpleWorker
bool run_cell()
{
- SigBit bit_a = sigmap(equiv_cell->getPort("\\A")).to_single_sigbit();
- SigBit bit_b = sigmap(equiv_cell->getPort("\\B")).to_single_sigbit();
+ SigBit bit_a = sigmap(equiv_cell->getPort("\\A")).as_bit();
+ SigBit bit_b = sigmap(equiv_cell->getPort("\\B")).as_bit();
int ez_context = ez->frozen_literal();
if (satgen.model_undef)
@@ -314,7 +314,7 @@ struct EquivSimplePass : public Pass {
for (auto cell : module->selected_cells())
if (cell->type == "$equiv" && cell->getPort("\\A") != cell->getPort("\\B")) {
- auto bit = sigmap(cell->getPort("\\Y").to_single_sigbit());
+ auto bit = sigmap(cell->getPort("\\Y").as_bit());
auto bit_group = bit;
if (!nogroup && bit_group.wire)
bit_group.offset = 0;
diff --git a/passes/fsm/fsm_opt.cc b/passes/fsm/fsm_opt.cc
index 7322368c..a7cc95ff 100644
--- a/passes/fsm/fsm_opt.cc
+++ b/passes/fsm/fsm_opt.cc
@@ -78,7 +78,7 @@ struct FsmOpt
bool signal_is_unused(RTLIL::SigSpec sig)
{
- RTLIL::SigBit bit = sig.to_single_sigbit();
+ RTLIL::SigBit bit = sig.as_bit();
if (bit.wire == NULL || bit.wire->attributes.count("\\unused_bits") == 0)
return false;
diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc
index ca784890..ebdf2ed5 100644
--- a/passes/sat/expose.cc
+++ b/passes/sat/expose.cc
@@ -116,7 +116,7 @@ void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::De
info.cell = it.second;
if (info.cell->type == "$dff") {
- info.bit_clk = sigmap(info.cell->getPort("\\CLK")).to_single_sigbit();
+ info.bit_clk = sigmap(info.cell->getPort("\\CLK")).as_bit();
info.clk_polarity = info.cell->parameters.at("\\CLK_POLARITY").as_bool();
std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->getPort("\\D")).to_sigbit_vector();
std::vector<RTLIL::SigBit> sig_q = sigmap(info.cell->getPort("\\Q")).to_sigbit_vector();
@@ -128,8 +128,8 @@ void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::De
}
if (info.cell->type == "$adff") {
- info.bit_clk = sigmap(info.cell->getPort("\\CLK")).to_single_sigbit();
- info.bit_arst = sigmap(info.cell->getPort("\\ARST")).to_single_sigbit();
+ info.bit_clk = sigmap(info.cell->getPort("\\CLK")).as_bit();
+ info.bit_arst = sigmap(info.cell->getPort("\\ARST")).as_bit();
info.clk_polarity = info.cell->parameters.at("\\CLK_POLARITY").as_bool();
info.arst_polarity = info.cell->parameters.at("\\ARST_POLARITY").as_bool();
std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->getPort("\\D")).to_sigbit_vector();
@@ -144,21 +144,21 @@ void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::De
}
if (info.cell->type == "$_DFF_N_" || info.cell->type == "$_DFF_P_") {
- info.bit_clk = sigmap(info.cell->getPort("\\C")).to_single_sigbit();
+ info.bit_clk = sigmap(info.cell->getPort("\\C")).as_bit();
info.clk_polarity = info.cell->type == "$_DFF_P_";
- info.bit_d = sigmap(info.cell->getPort("\\D")).to_single_sigbit();
- bit_info[sigmap(info.cell->getPort("\\Q")).to_single_sigbit()] = info;
+ info.bit_d = sigmap(info.cell->getPort("\\D")).as_bit();
+ bit_info[sigmap(info.cell->getPort("\\Q")).as_bit()] = info;
continue;
}
if (info.cell->type.size() == 10 && info.cell->type.substr(0, 6) == "$_DFF_") {
- info.bit_clk = sigmap(info.cell->getPort("\\C")).to_single_sigbit();
- info.bit_arst = sigmap(info.cell->getPort("\\R")).to_single_sigbit();
+ info.bit_clk = sigmap(info.cell->getPort("\\C")).as_bit();
+ info.bit_arst = sigmap(info.cell->getPort("\\R")).as_bit();
info.clk_polarity = info.cell->type[6] == 'P';
info.arst_polarity = info.cell->type[7] == 'P';
info.arst_value = info.cell->type[0] == '1' ? RTLIL::State::S1 : RTLIL::State::S0;
- info.bit_d = sigmap(info.cell->getPort("\\D")).to_single_sigbit();
- bit_info[sigmap(info.cell->getPort("\\Q")).to_single_sigbit()] = info;
+ info.bit_d = sigmap(info.cell->getPort("\\D")).as_bit();
+ bit_info[sigmap(info.cell->getPort("\\Q")).as_bit()] = info;
continue;
}
}