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authorClifford Wolf <clifford@clifford.at>2014-08-16 23:50:36 +0200
committerClifford Wolf <clifford@clifford.at>2014-08-16 23:50:36 +0200
commit7f734ecc098a2a113ced835cefc9d4e1982f08d0 (patch)
tree0e73ad74bd4602da7a6a1a3b264e1842deccac18 /passes
parentf82c978e08604c596b034fb6e74ac34c78b9364b (diff)
Added module->uniquify()
Diffstat (limited to 'passes')
-rw-r--r--passes/cmds/splitnets.cc5
-rw-r--r--passes/fsm/fsm_map.cc6
2 files changed, 2 insertions, 9 deletions
diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc
index a3daf239..cef0a272 100644
--- a/passes/cmds/splitnets.cc
+++ b/passes/cmds/splitnets.cc
@@ -46,10 +46,7 @@ struct SplitnetsWorker
if (format.size() > 1)
new_wire_name += format.substr(1, 1);
- while (module->count_id(new_wire_name) > 0)
- new_wire_name += "_";
-
- RTLIL::Wire *new_wire = module->addWire(new_wire_name, width);
+ RTLIL::Wire *new_wire = module->addWire(module->uniquify(new_wire_name), width);
new_wire->port_id = wire->port_id;
new_wire->port_input = wire->port_input;
new_wire->port_output = wire->port_output;
diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc
index 60580eb4..ab6d5671 100644
--- a/passes/fsm/fsm_map.cc
+++ b/passes/fsm/fsm_map.cc
@@ -163,11 +163,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
// create state register
- std::string state_wire_name = fsm_cell->parameters["\\NAME"].decode_string();
- while (module->count_id(state_wire_name) > 0)
- state_wire_name += "_";
-
- RTLIL::Wire *state_wire = module->addWire(state_wire_name, fsm_data.state_bits);
+ RTLIL::Wire *state_wire = module->addWire(module->uniquify(fsm_cell->parameters["\\NAME"].decode_string()), fsm_data.state_bits);
RTLIL::Wire *next_state_wire = module->addWire(NEW_ID, fsm_data.state_bits);
RTLIL::Cell *state_dff = module->addCell(NEW_ID, "");