diff options
| author | Johann Glaser <Johann.Glaser@gmx.at> | 2013-03-18 22:05:21 +0100 |
|---|---|---|
| committer | Johann Glaser <Johann.Glaser@gmx.at> | 2013-03-18 22:05:21 +0100 |
| commit | a4e2c887f12e6bf713ea77c7a2a687b3cd0b984a (patch) | |
| tree | 975e962a170c8f8e3fe53e991ac133e5d68078a4 /passes | |
| parent | 15ad2db8fc4e608d05e87d4d447cb0a5f1081c95 (diff) | |
also optimize single-bit "$mux" cells in pass "opt_const", added suggestions
for more optimizations
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/opt/opt_const.cc | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index 4d00807a..90950096 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -113,7 +113,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module) if (input.match("0 ")) ACTION_DO("\\Y", input.extract(0, 1)); } - if (cell->type == "$_MUX_") { + if (cell->type == "$_MUX_" ||(cell->type == "$mux" && cell->parameters["\\WIDTH"].as_int() == 1)) { RTLIL::SigSpec input; input.append(cell->connections["\\S"]); input.append(cell->connections["\\B"]); @@ -125,6 +125,10 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module) if (input.match(" 1")) ACTION_DO("\\Y", input.extract(1, 1)); #ifdef MUX_UNDEF_SEL_TO_UNDEF_RESULTS if (input.match("01 ")) ACTION_DO("\\Y", input.extract(0, 1)); + // TODO: "0 " -> replace with "B AND S" gate + // TODO: " 1 " -> replace with "A OR S" gate + // TODO: "1 " -> replace with "B OR !S" gate + // TODO: " 0 " -> replace with "A AND !S" gate if (input.match(" *")) ACTION_DO_Y(x); #endif } |