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authorClifford Wolf <clifford@clifford.at>2013-12-29 17:39:49 +0100
committerClifford Wolf <clifford@clifford.at>2013-12-29 17:39:49 +0100
commitbf607df6d57c3976880004192129eff8b1c0d0a9 (patch)
tree3bf063e9d2b7a3bb1b0efa89fd184a900f34dffc /passes
parent74d0de3b74cdf5d41eacd588d69488290549fd7e (diff)
Fixed undef extend for bitwise binary ops (bugs in simplemap and satgen)
Diffstat (limited to 'passes')
-rw-r--r--passes/techmap/simplemap.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc
index 2480cf28..e06a80bb 100644
--- a/passes/techmap/simplemap.cc
+++ b/passes/techmap/simplemap.cc
@@ -77,11 +77,11 @@ static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
int width = cell->parameters.at("\\Y_WIDTH").as_int();
RTLIL::SigSpec sig_a = cell->connections.at("\\A");
- sig_a.extend(width, cell->parameters.at("\\A_SIGNED").as_bool());
+ sig_a.extend_u0(width, cell->parameters.at("\\A_SIGNED").as_bool());
sig_a.expand();
RTLIL::SigSpec sig_b = cell->connections.at("\\B");
- sig_b.extend(width, cell->parameters.at("\\B_SIGNED").as_bool());
+ sig_b.extend_u0(width, cell->parameters.at("\\B_SIGNED").as_bool());
sig_b.expand();
RTLIL::SigSpec sig_y = cell->connections.at("\\Y");